mirror of https://github.com/YosysHQ/yosys.git
93 lines
3.0 KiB
Verilog
93 lines
3.0 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module \$shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
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parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i;
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wire [A_WIDTH-1:0] A_forward;
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assign A_forward[A_WIDTH-1] = A[A_WIDTH-1];
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for (i = A_WIDTH-2; i >= 0; i = i - 1)
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if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
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assign A_forward[i] = A_forward[i+1];
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else
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assign A_forward[i] = A[i];
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wire [A_WIDTH-1:0] A_without_x;
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assign A_without_x[0] = A_forward[0];
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for (i = 1; i < A_WIDTH; i = i + 1)
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if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
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assign A_without_x[i] = A_without_x[i-1];
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else
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assign A_without_x[i] = A[i];
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if (B_SIGNED) begin
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if (B_WIDTH < 4 || A_WIDTH <= 4)
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wire _TECHMAP_FAIL_ = 1;
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else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
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// Optimisation to remove B_SIGNED if sign bit of B is constant-0
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\$__XILINX_SHIFTX #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(0),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH-1'd1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
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);
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end
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else begin
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if (B_WIDTH < 3 || A_WIDTH <= 4)
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wire _TECHMAP_FAIL_ = 1;
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else
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\$__XILINX_SHIFTX #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_without_x), .B(B), .Y(Y)
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);
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end
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endgenerate
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endmodule
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module \$_MUX4_ (A, B, C, D, S, T, Y);
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input A, B, C, D, S, T;
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output Y;
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assign Y = T ? (S ? D : C) :
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(S ? B : A);
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endmodule
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