mirror of https://github.com/YosysHQ/yosys.git
675 lines
22 KiB
C++
675 lines
22 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "libparse.h"
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#include <string.h>
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#include <errno.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct cell_mapping {
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IdString cell_name;
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std::map<std::string, char> ports;
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};
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static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
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static void logmap(IdString dff)
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{
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff.c_str());
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} else {
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log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
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bool first = true;
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for (auto &port : cell_mappings[dff].ports) {
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char arg[3] = { port.second, 0, 0 };
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if ('a' <= arg[0] && arg[0] <= 'z')
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arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
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else
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arg[1] = arg[0], arg[0] = ' ';
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log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
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first = false;
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}
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log(");\n");
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}
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}
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static void logmap_all()
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{
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logmap(ID($_DFF_N_));
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logmap(ID($_DFF_P_));
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logmap(ID($_DFF_NN0_));
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logmap(ID($_DFF_NN1_));
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logmap(ID($_DFF_NP0_));
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logmap(ID($_DFF_NP1_));
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logmap(ID($_DFF_PN0_));
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logmap(ID($_DFF_PN1_));
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logmap(ID($_DFF_PP0_));
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logmap(ID($_DFF_PP1_));
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logmap(ID($_DFFSR_NNN_));
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logmap(ID($_DFFSR_NNP_));
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logmap(ID($_DFFSR_NPN_));
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logmap(ID($_DFFSR_NPP_));
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logmap(ID($_DFFSR_PNN_));
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logmap(ID($_DFFSR_PNP_));
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logmap(ID($_DFFSR_PPN_));
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logmap(ID($_DFFSR_PPP_));
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}
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static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
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{
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if (cell == NULL || attr == NULL || attr->value.empty())
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return false;
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std::string value = attr->value;
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for (size_t pos = value.find_first_of("\" \t()"); pos != std::string::npos; pos = value.find_first_of("\" \t()"))
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value.erase(pos, 1);
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if (value[value.size()-1] == '\'') {
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pin_name = value.substr(0, value.size()-1);
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pin_pol = false;
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} else if (value[0] == '!') {
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pin_name = value.substr(1, value.size()-1);
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pin_pol = false;
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} else {
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pin_name = value;
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pin_pol = true;
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}
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for (auto child : cell->children)
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if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name)
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return true;
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/* If we end up here, the pin specified in the attribute does not exist, which is an error,
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or, the attribute contains an expression which we do not yet support.
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For now, we'll simply produce a warning to let the user know something is up.
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*/
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if (pin_name.find_first_of("^*|&") == std::string::npos) {
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log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
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}
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else {
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log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
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}
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return false;
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}
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static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode)
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{
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *dn = cell->find("dont_use");
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if (dn != NULL && dn->value == "true")
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continue;
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LibertyAst *ff = cell->find("ff");
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if (ff == NULL)
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continue;
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std::string cell_clk_pin, cell_rst_pin, cell_next_pin;
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bool cell_clk_pol, cell_rst_pol, cell_next_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_pin(cell, ff->find("next_state"), cell_next_pin, cell_next_pol))
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continue;
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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if (has_reset && rstval == true) {
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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if (has_reset)
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this_cell_ports[cell_rst_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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double area = 0;
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LibertyAst *ar = cell->find("area");
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if (ar != NULL && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != NULL) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != NULL) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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if (prepare_mode) {
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cell_mappings[cell_type].cell_name = cell_type;
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cell_mappings[cell_type].ports["C"] = 'C';
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if (has_reset)
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cell_mappings[cell_type].ports["R"] = 'R';
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cell_mappings[cell_type].ports["D"] = 'D';
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cell_mappings[cell_type].ports["Q"] = 'Q';
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} else {
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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}
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static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode)
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{
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *dn = cell->find("dont_use");
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if (dn != NULL && dn->value == "true")
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continue;
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LibertyAst *ff = cell->find("ff");
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if (ff == NULL)
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continue;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_pin(cell, ff->find("next_state"), cell_next_pin, cell_next_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol)
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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this_cell_ports[cell_set_pin] = 'S';
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this_cell_ports[cell_clr_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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double area = 0;
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LibertyAst *ar = cell->find("area");
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if (ar != NULL && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != NULL) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != NULL) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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if (prepare_mode) {
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cell_mappings[cell_type].cell_name = cell_type;
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cell_mappings[cell_type].ports["C"] = 'C';
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cell_mappings[cell_type].ports["S"] = 'S';
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cell_mappings[cell_type].ports["R"] = 'R';
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cell_mappings[cell_type].ports["D"] = 'D';
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cell_mappings[cell_type].ports["Q"] = 'Q';
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} else {
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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}
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static bool expand_cellmap_worker(std::string from, std::string to, std::string inv)
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{
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if (cell_mappings.count(to) > 0)
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return false;
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports) {
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char cmp_ch = it.second;
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if ('a' <= cmp_ch && cmp_ch <= 'z')
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cmp_ch -= 'a' - 'A';
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if (inv.find(cmp_ch) == std::string::npos)
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continue;
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if ('a' <= it.second && it.second <= 'z')
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it.second -= 'a' - 'A';
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else if ('A' <= it.second && it.second <= 'Z')
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it.second += 'a' - 'A';
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}
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return true;
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}
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static bool expand_cellmap(std::string pattern, std::string inv)
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{
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std::vector<std::pair<std::string, std::string>> from_to_list;
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bool return_status = false;
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for (auto &it : cell_mappings) {
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std::string from = it.first.str(), to = it.first.str();
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if (from.size() != pattern.size())
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continue;
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for (size_t i = 0; i < from.size(); i++) {
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if (pattern[i] == '*') {
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to[i] = from[i] == 'P' ? 'N' :
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from[i] == 'N' ? 'P' :
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from[i] == '1' ? '0' :
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from[i] == '0' ? '1' : '*';
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} else
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if (pattern[i] != '?' && pattern[i] != from[i])
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goto pattern_failed;
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}
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from_to_list.push_back(std::pair<std::string, std::string>(from, to));
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pattern_failed:;
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}
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for (auto &it : from_to_list)
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return_status = return_status || expand_cellmap_worker(it.first, it.second, inv);
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return return_status;
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}
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static void map_sr_to_arst(IdString from, IdString to)
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{
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
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char from_set_pol = from[9];
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char from_clr_pol = from[10];
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char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
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char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
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char to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports)
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{
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bool is_set_pin = it.second == 'S' || it.second == 's';
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bool is_clr_pin = it.second == 'R' || it.second == 'r';
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if (!is_set_pin && !is_clr_pin)
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continue;
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if ((to_rst_val == '0' && is_set_pin) || (to_rst_val == '1' && is_clr_pin))
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{
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// this is the unused set/clr pin -- deactivate it
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if (is_set_pin)
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it.second = (from_set_pol == 'P') == (it.second == 'S') ? '0' : '1';
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else
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it.second = (from_clr_pol == 'P') == (it.second == 'R') ? '0' : '1';
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}
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else
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{
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// this is the used set/clr pin -- rename it to 'reset'
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if (it.second == 'S')
|
|
it.second = 'R';
|
|
if (it.second == 's')
|
|
it.second = 'r';
|
|
}
|
|
}
|
|
}
|
|
|
|
static void map_adff_to_dff(IdString from, IdString to)
|
|
{
|
|
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
|
|
return;
|
|
|
|
char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
|
|
char from_rst_pol = from[7];
|
|
char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
|
|
|
|
log_assert(from_clk_pol == to_clk_pol);
|
|
|
|
log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
|
|
cell_mappings[to].cell_name = cell_mappings[from].cell_name;
|
|
cell_mappings[to].ports = cell_mappings[from].ports;
|
|
|
|
for (auto &it : cell_mappings[to].ports) {
|
|
if (it.second == 'S' || it.second == 'R')
|
|
it.second = from_rst_pol == 'P' ? '0' : '1';
|
|
if (it.second == 's' || it.second == 'r')
|
|
it.second = from_rst_pol == 'P' ? '1' : '0';
|
|
}
|
|
}
|
|
|
|
static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare_mode)
|
|
{
|
|
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
|
|
|
|
dict<SigBit, pool<Cell*>> notmap;
|
|
SigMap sigmap(module);
|
|
|
|
std::vector<RTLIL::Cell*> cell_list;
|
|
for (auto &it : module->cells_) {
|
|
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
|
|
cell_list.push_back(it.second);
|
|
if (it.second->type == ID($_NOT_))
|
|
notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second);
|
|
}
|
|
|
|
std::map<std::string, int> stats;
|
|
for (auto cell : cell_list)
|
|
{
|
|
auto cell_type = cell->type;
|
|
auto cell_name = cell->name;
|
|
auto cell_connections = cell->connections();
|
|
std::string src = cell->get_src_attribute();
|
|
|
|
module->remove(cell);
|
|
|
|
cell_mapping &cm = cell_mappings[cell_type];
|
|
RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : cm.cell_name);
|
|
|
|
new_cell->set_src_attribute(src);
|
|
|
|
bool has_q = false, has_qn = false;
|
|
for (auto &port : cm.ports) {
|
|
if (port.second == 'Q') has_q = true;
|
|
if (port.second == 'q') has_qn = true;
|
|
}
|
|
|
|
for (auto &port : cm.ports) {
|
|
RTLIL::SigSpec sig;
|
|
if ('A' <= port.second && port.second <= 'Z') {
|
|
sig = cell_connections[std::string("\\") + port.second];
|
|
} else
|
|
if (port.second == 'q') {
|
|
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
|
sig = module->addWire(NEW_ID, GetSize(old_sig));
|
|
if (has_q && has_qn) {
|
|
for (auto &it : notmap[sigmap(old_sig)]) {
|
|
module->connect(it->getPort(ID(Y)), sig);
|
|
it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig)));
|
|
}
|
|
} else {
|
|
module->addNotGate(NEW_ID, sig, old_sig);
|
|
}
|
|
} else
|
|
if ('a' <= port.second && port.second <= 'z') {
|
|
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
|
sig = module->NotGate(NEW_ID, sig);
|
|
} else
|
|
if (port.second == '0' || port.second == '1') {
|
|
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
|
|
} else
|
|
if (port.second == 0) {
|
|
sig = module->addWire(NEW_ID);
|
|
} else
|
|
log_abort();
|
|
new_cell->setPort("\\" + port.first, sig);
|
|
}
|
|
|
|
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
|
|
}
|
|
|
|
for (auto &stat: stats)
|
|
log(stat.first.c_str(), stat.second);
|
|
}
|
|
|
|
struct DfflibmapPass : public Pass {
|
|
DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
log("\n");
|
|
log(" dfflibmap [-prepare] -liberty <file> [selection]\n");
|
|
log("\n");
|
|
log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
|
|
log("library specified in the given liberty file.\n");
|
|
log("\n");
|
|
log("This pass may add inverters as needed. Therefore it is recommended to\n");
|
|
log("first run this pass and then map the logic paths to the target technology.\n");
|
|
log("\n");
|
|
log("When called with -prepare, this command will convert the internal FF cells\n");
|
|
log("to the internal cell types that best match the cells found in the given\n");
|
|
log("liberty file.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
|
|
|
|
std::string liberty_file;
|
|
bool prepare_mode = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
std::string arg = args[argidx];
|
|
if (arg == "-liberty" && argidx+1 < args.size()) {
|
|
liberty_file = args[++argidx];
|
|
rewrite_filename(liberty_file);
|
|
continue;
|
|
}
|
|
if (arg == "-prepare") {
|
|
prepare_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
if (liberty_file.empty())
|
|
log_cmd_error("Missing `-liberty liberty_file' option!\n");
|
|
|
|
std::ifstream f;
|
|
f.open(liberty_file.c_str());
|
|
if (f.fail())
|
|
log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
|
|
LibertyParser libparser(f);
|
|
f.close();
|
|
|
|
find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, prepare_mode);
|
|
|
|
find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, prepare_mode);
|
|
find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, prepare_mode);
|
|
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, prepare_mode);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, prepare_mode);
|
|
|
|
// try to implement as many cells as possible just by inverting
|
|
// the SET and RESET pins. If necessary, implement cell types
|
|
// by inverting both D and Q. Only invert clock pins if there
|
|
// is no other way of implementing the cell.
|
|
while (1)
|
|
{
|
|
if (expand_cellmap("$_DFF_?*?_", "R") ||
|
|
expand_cellmap("$_DFFSR_?*?_", "S") ||
|
|
expand_cellmap("$_DFFSR_??*_", "R"))
|
|
continue;
|
|
|
|
if (expand_cellmap("$_DFF_??*_", "DQ"))
|
|
continue;
|
|
|
|
if (expand_cellmap("$_DFF_*_", "C") ||
|
|
expand_cellmap("$_DFF_*??_", "C") ||
|
|
expand_cellmap("$_DFFSR_*??_", "C"))
|
|
continue;
|
|
|
|
break;
|
|
}
|
|
|
|
map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN0_));
|
|
map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN1_));
|
|
map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP0_));
|
|
map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP1_));
|
|
map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN0_));
|
|
map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN1_));
|
|
map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP0_));
|
|
map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP1_));
|
|
|
|
map_adff_to_dff(ID($_DFF_NN0_), ID($_DFF_N_));
|
|
map_adff_to_dff(ID($_DFF_NN1_), ID($_DFF_N_));
|
|
map_adff_to_dff(ID($_DFF_NP0_), ID($_DFF_N_));
|
|
map_adff_to_dff(ID($_DFF_NP1_), ID($_DFF_N_));
|
|
map_adff_to_dff(ID($_DFF_PN0_), ID($_DFF_P_));
|
|
map_adff_to_dff(ID($_DFF_PN1_), ID($_DFF_P_));
|
|
map_adff_to_dff(ID($_DFF_PP0_), ID($_DFF_P_));
|
|
map_adff_to_dff(ID($_DFF_PP1_), ID($_DFF_P_));
|
|
|
|
log(" final dff cell mappings:\n");
|
|
logmap_all();
|
|
|
|
for (auto &it : design->modules_)
|
|
if (design->selected(it.second) && !it.second->get_blackbox_attribute())
|
|
dfflibmap(design, it.second, prepare_mode);
|
|
|
|
cell_mappings.clear();
|
|
}
|
|
} DfflibmapPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|