yosys/backends/verilog
Marcelina Kościelnicka ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output.
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
2021-08-01 19:11:29 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc backend/verilog: Add alternate mode for transparent read port output. 2021-08-01 19:11:29 +02:00