mirror of https://github.com/YosysHQ/yosys.git
31 lines
733 B
Verilog
31 lines
733 B
Verilog
//-----------------------------------------------------
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// Design Name : dff_async_reset
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// File Name : dff_async_reset.v
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// Function : D flip-flop async reset
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module dff_async_reset (
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data , // Data Input
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clk , // Clock Input
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reset , // Reset input
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q // Q output
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);
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//-----------Input Ports---------------
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input data, clk, reset ;
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//-----------Output Ports---------------
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output q;
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//------------Internal Variables--------
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reg q;
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//-------------Code Starts Here---------
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always @ ( posedge clk or negedge reset)
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if (~reset) begin
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q <= 1'b0;
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end else begin
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q <= data;
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end
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endmodule //End Of Module dff_async_reset
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