whitequark f8d5920a7e Merge pull request #1604 from whitequark/unify-ram-naming ... Harmonize BRAM/LUTRAM descriptions across all of Yosys		2020-01-02 21:06:17 +00:00
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Makefile.inc	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
anlogic_eqn.cc	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
anlogic_fixcarry.cc	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00
arith_map.v	Fix missing newline at end of file	2019-08-22 18:09:37 +02:00
cells_map.v	Fix anlogic async flop mapping	2020-01-01 08:43:16 -08:00
cells_sim.v	make note that it is for latch mode	2019-09-18 17:48:16 +02:00
eagle_bb.v	Revert "Leave only real black box cells"	2018-12-17 23:20:40 +08:00
lutram_init_16x4.vh	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
lutrams.txt	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
lutrams_map.v	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
synth_anlogic.cc	Merge pull request #1604 from whitequark/unify-ram-naming	2020-01-02 21:06:17 +00:00