mirror of https://github.com/YosysHQ/yosys.git
78 lines
1.3 KiB
Verilog
78 lines
1.3 KiB
Verilog
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module GND(G);
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output G = 0;
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endmodule
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module INV(O, I);
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input I;
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output O = !I;
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endmodule
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module LUT1(O, I0);
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parameter INIT = 0;
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input I0;
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wire [1:0] lutdata = INIT;
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wire [0:0] idx = { I0 };
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output O = lutdata[idx];
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endmodule
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module LUT2(O, I0, I1);
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parameter INIT = 0;
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input I0, I1;
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wire [3:0] lutdata = INIT;
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wire [1:0] idx = { I1, I0 };
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output O = lutdata[idx];
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endmodule
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module LUT3(O, I0, I1, I2);
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parameter INIT = 0;
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input I0, I1, I2;
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wire [7:0] lutdata = INIT;
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wire [2:0] idx = { I2, I1, I0 };
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output O = lutdata[idx];
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endmodule
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module LUT4(O, I0, I1, I2, I3);
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parameter INIT = 0;
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input I0, I1, I2, I3;
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wire [15:0] lutdata = INIT;
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wire [3:0] idx = { I3, I2, I1, I0 };
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output O = lutdata[idx];
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endmodule
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module LUT5(O, I0, I1, I2, I3, I4);
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parameter INIT = 0;
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input I0, I1, I2, I3, I4;
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wire [31:0] lutdata = INIT;
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wire [4:0] idx = { I4, I3, I2, I1, I0 };
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output O = lutdata[idx];
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endmodule
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module LUT6(O, I0, I1, I2, I3, I4, I5);
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parameter INIT = 0;
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input I0, I1, I2, I3, I4, I5;
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wire [63:0] lutdata = INIT;
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wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
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output O = lutdata[idx];
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endmodule
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module MUXCY(O, CI, DI, S);
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input CI, DI, S;
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output O = S ? CI : DI;
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endmodule
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module MUXF7(O, I0, I1, S);
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input I0, I1, S;
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output O = S ? I1 : I0;
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endmodule
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module VCC(P);
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output P = 1;
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endmodule
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module XORCY(O, CI, LI);
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input CI, LI;
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output O = CI ^ LI;
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endmodule
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