mirror of https://github.com/YosysHQ/yosys.git
304 lines
8.9 KiB
C++
304 lines
8.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] Tarjan's strongly connected components algorithm
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// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146–160, doi:10.1137/0201010
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// http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SccWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap;
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CellTypes ct;
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std::set<RTLIL::Cell*> workQueue;
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std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> cellToNextCell;
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std::map<RTLIL::Cell*, RTLIL::SigSpec> cellToPrevSig, cellToNextSig;
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std::map<RTLIL::Cell*, std::pair<int, int>> cellLabels;
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std::map<RTLIL::Cell*, int> cellDepth;
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std::set<RTLIL::Cell*> cellsOnStack;
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std::vector<RTLIL::Cell*> cellStack;
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int labelCounter;
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std::map<RTLIL::Cell*, int> cell2scc;
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std::vector<std::set<RTLIL::Cell*>> sccList;
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void run(RTLIL::Cell *cell, int depth, int maxDepth)
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{
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log_assert(workQueue.count(cell) > 0);
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workQueue.erase(cell);
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cellLabels[cell] = std::pair<int, int>(labelCounter, labelCounter);
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labelCounter++;
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cellsOnStack.insert(cell);
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cellStack.push_back(cell);
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if (maxDepth >= 0)
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cellDepth[cell] = depth;
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for (auto nextCell : cellToNextCell[cell])
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if (cellLabels.count(nextCell) == 0) {
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run(nextCell, depth+1, maxDepth);
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cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
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} else
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if (cellsOnStack.count(nextCell) > 0 && (maxDepth < 0 || cellDepth[nextCell] + maxDepth > depth)) {
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cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
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}
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if (cellLabels[cell].first == cellLabels[cell].second)
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{
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if (cellStack.back() == cell)
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{
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cellStack.pop_back();
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cellsOnStack.erase(cell);
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}
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else
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{
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log("Found an SCC:");
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std::set<RTLIL::Cell*> scc;
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while (cellsOnStack.count(cell) > 0) {
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RTLIL::Cell *c = cellStack.back();
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cellStack.pop_back();
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cellsOnStack.erase(c);
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log(" %s", RTLIL::id2cstr(c->name));
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cell2scc[c] = sccList.size();
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scc.insert(c);
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}
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sccList.push_back(scc);
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log("\n");
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}
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}
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}
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SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool allCellTypes, int maxDepth) : design(design), module(module), sigmap(module)
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{
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
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return;
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}
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if (allCellTypes) {
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ct.setup(design);
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} else {
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ct.setup_internals();
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ct.setup_stdcells();
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}
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SigPool selectedSignals;
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SigSet<RTLIL::Cell*> sigToNextCells;
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for (auto &it : module->wires_)
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if (design->selected(module, it.second))
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selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (!design->selected(module, cell))
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continue;
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if (!allCellTypes && !ct.cell_known(cell->type))
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continue;
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workQueue.insert(cell);
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RTLIL::SigSpec inputSignals, outputSignals;
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for (auto &conn : cell->connections())
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{
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bool isInput = true, isOutput = true;
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if (ct.cell_known(cell->type)) {
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isInput = ct.cell_input(cell->type, conn.first);
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isOutput = ct.cell_output(cell->type, conn.first);
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}
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RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second));
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sig.sort_and_unify();
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if (isInput)
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inputSignals.append(sig);
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if (isOutput)
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outputSignals.append(sig);
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}
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inputSignals.sort_and_unify();
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outputSignals.sort_and_unify();
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cellToPrevSig[cell] = inputSignals;
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cellToNextSig[cell] = outputSignals;
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sigToNextCells.insert(inputSignals, cell);
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}
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for (auto cell : workQueue)
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cellToNextCell[cell] = sigToNextCells.find(cellToNextSig[cell]);
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labelCounter = 0;
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cellLabels.clear();
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while (workQueue.size() > 0) {
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RTLIL::Cell *cell = *workQueue.begin();
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log_assert(cellStack.size() == 0);
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cellDepth.clear();
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run(cell, 0, maxDepth);
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}
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log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name));
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}
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void select(RTLIL::Selection &sel)
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{
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for (int i = 0; i < int(sccList.size()); i++)
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{
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std::set<RTLIL::Cell*> &cells = sccList[i];
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RTLIL::SigSpec prevsig, nextsig, sig;
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for (auto cell : cells) {
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sel.selected_members[module->name].insert(cell->name);
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prevsig.append(cellToPrevSig[cell]);
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nextsig.append(cellToNextSig[cell]);
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}
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prevsig.sort_and_unify();
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nextsig.sort_and_unify();
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sig = prevsig.extract(nextsig);
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for (auto &chunk : sig.chunks())
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if (chunk.wire != NULL)
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sel.selected_members[module->name].insert(chunk.wire->name);
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}
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}
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};
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struct SccPass : public Pass {
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SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" scc [options] [selection]\n");
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log("\n");
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log("This command identifies strongly connected components (aka logic loops) in the\n");
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log("design.\n");
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log("\n");
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log(" -max_depth <num>\n");
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log(" limit to loops not longer than the specified number of cells. This can\n");
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log(" e.g. be useful in identifying local loops in a module that turns out\n");
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log(" to be one gigantic SCC.\n");
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log("\n");
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log(" -all_cell_types\n");
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log(" Usually this command only considers internal non-memory cells. With\n");
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log(" this option set, all cells are considered. For unknown cells all ports\n");
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log(" are assumed to be bidirectional 'inout' ports.\n");
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log("\n");
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log(" -set_attr <name> <value>\n");
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log(" -set_cell_attr <name> <value>\n");
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log(" -set_wire_attr <name> <value>\n");
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log(" set the specified attribute on all cells and/or wires that are part of\n");
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log(" a logic loop. the special token {} in the value is replaced with a\n");
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log(" unique identifier for the logic loop.\n");
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log("\n");
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log(" -select\n");
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log(" replace the current selection with a selection of all cells and wires\n");
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log(" that are part of a found logic loop\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::map<std::string, std::string> setCellAttr, setWireAttr;
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bool allCellTypes = false;
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bool selectMode = false;
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int maxDepth = -1;
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log_header("Executing SCC pass (detecting logic loops).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-max_depth" && argidx+1 < args.size()) {
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maxDepth = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-all_cell_types") {
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allCellTypes = true;
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continue;
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}
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if (args[argidx] == "-set_attr" && argidx+2 < args.size()) {
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setCellAttr[args[argidx+1]] = args[argidx+2];
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setWireAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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continue;
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}
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if (args[argidx] == "-set_cell_attr" && argidx+2 < args.size()) {
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setCellAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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continue;
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}
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if (args[argidx] == "-set_wire_attr" && argidx+2 < args.size()) {
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setWireAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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continue;
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}
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if (args[argidx] == "-select") {
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selectMode = true;
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continue;
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}
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break;
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}
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int origSelectPos = design->selection_stack.size() - 1;
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extra_args(args, argidx, design);
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if (setCellAttr.size() > 0 || setWireAttr.size() > 0)
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log_cmd_error("The -set*_attr options are not implemented at the moment!\n");
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RTLIL::Selection newSelection(false);
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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{
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SccWorker worker(design, mod_it.second, allCellTypes, maxDepth);
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if (selectMode)
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worker.select(newSelection);
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}
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if (selectMode) {
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log_assert(origSelectPos >= 0);
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design->selection_stack[origSelectPos] = newSelection;
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design->selection_stack[origSelectPos].optimize(design);
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}
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}
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} SccPass;
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PRIVATE_NAMESPACE_END
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