mirror of https://github.com/YosysHQ/yosys.git
394 lines
8.4 KiB
Plaintext
394 lines
8.4 KiB
Plaintext
log -header "Test basic s?(a+b):a pattern gets transformed (a,b module inputs)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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input wire s;
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output wire [3:0] y;
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assign y = s ? (a + b) : a;
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -header "Test basic s?(a+b):a pattern with intermediate var gets transformed (a,b module inputs)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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input wire s;
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output wire [3:0] y;
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wire [3:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -header "Test basic s?(a+b):a pattern gets transformed (a is driven by a cell)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a_, b, s, y);
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input wire [3:0] a_;
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wire [3:0] a = ~a_;
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input wire [3:0] b;
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input wire s;
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output wire [3:0] y;
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wire [3:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -header "Test basic s?(a+b):a pattern gets transformed (b is driven by a cell, output consumed by a cell)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b_, f, s, y_);
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input wire [3:0] a;
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input wire [3:0] b_;
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input wire [3:0] f;
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wire [3:0] b = b_ ^ f;
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input wire s;
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wire [3:0] y;
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output wire [3:0] y_;
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assign y_ = ~y;
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wire [3:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -header "Test no transform when a+b has more fanouts (module output)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, ab, s, y);
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input wire [2:0] a;
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input wire [2:0] b;
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output wire [2:0] ab;
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output wire [2:0] y;
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input wire s;
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assign ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-none t:$add %co1 %a w:y %i
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -header "Test no transform when a+b has more fanouts (single bit, cell)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y, z);
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input wire [2:0] a;
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input wire [2:0] b;
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output wire [2:0] y;
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input wire s;
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wire [2:0] ab = a + b;
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assign y = s ? ab : a;
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output wire [2:0] z = !ab[1];
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endmodule
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EOF
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check -assert
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copy top orig
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cd top
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peepopt
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select -assert-none t:$add %co1 %a w:y %i
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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log Please fix all the designs below to use the miter/sat proof
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quit
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log -pop
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log -header "Test no transform when a+b width smaller than a's width"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire [2:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test no transform when (a+b) wider than a, adder’s a input is unsigned, a is not padded with zeros on the muxes input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire [3:0] ab = a + b;
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assign y = s ? ab : {a[2], a};
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test no transform when (a+b) wider than a, adder’s a input is signed, a is not sign-extended on the muxes input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire signed [3:0] ab = $signed(a) + $signed(b);
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assign y = s ? ab : {1'b0, a};
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test no transform when adder and mux not connected together but otherwise fitting transform. criteria"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire [3:0] ab = a + b;
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wire [3:0] ab_ = !a;
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assign y = s ? ab_ : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test transform when (a+b) wider than a, adder’s a input is unsigned, a padded with zeros on the muxes input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire [3:0] ab = a + b;
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assign y = s ? ab : {1'b0, a};
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test transform when (a+b) wider than a, adder’s a input is signed, a sign-extended on the muxes input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire signed [3:0] ab = $signed(a) + $signed(b);
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assign y = s ? ab : {a[2], a};
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$add %co1 %a w:y %i
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log -pop
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log -header "Test transform when pattern is s?a:(a+b)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire signed [3:0] ab = a + b;
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assign y = s ? a : ab;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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log -pop
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log -header "Test transform when pattern is a?(b+a):a"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [3:0] b;
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output wire [3:0] y;
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input wire s;
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wire signed [3:0] ab = b + a;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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log -pop
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log -header "Test transform when widths b > (a+b) > a"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [4:0] b;
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output wire [3:0] y;
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input wire s;
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wire signed [3:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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log -pop
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log -header "Test transform when widths (a+b) > a > b"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [2:0] a;
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input wire [3:0] b;
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output wire [4:0] y;
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input wire s;
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wire signed [4:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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log -pop
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log -header "Test transform when widths (a+b) > b > a"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [3:0] a;
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input wire [2:0] b;
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output wire [4:0] y;
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input wire s;
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wire signed [4:0] ab = a + b;
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assign y = s ? ab : a;
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endmodule
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EOF
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check -assert
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wreduce
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opt_clean
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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