mirror of https://github.com/YosysHQ/yosys.git
321 lines
9.1 KiB
Verilog
321 lines
9.1 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// See document PolarFire Family Fabric User Guide
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// section 4.1 for port list.
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//LSRAM true dual-port
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module $__LSRAM_TDP_ (...);
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parameter INIT = 0;
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parameter ADDR_BITS = 14;
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parameter OPTION_WIDTH_CONFIG = "A";
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parameter PORT_A_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_RD_USED = 0;
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parameter PORT_A_WR_USED = 0;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_RD_USED = 0;
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parameter PORT_B_WR_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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input PORT_A_CLK;
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input PORT_A_RD_EN;
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input [ADDR_BITS-1:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_B_CLK;
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input PORT_B_RD_EN;
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input [ADDR_BITS-1:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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`include "brams_defs.vh"
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// address wires
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wire [ADDR_BITS-1:0] A_address;
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wire [ADDR_BITS-1:0] B_address;
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assign A_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_A_ADDR : {PORT_A_ADDR, 2'b00};
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assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_B_ADDR : {PORT_B_ADDR, 2'b00};
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// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
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parameter PORT_A_RD_USED = 0;
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parameter PORT_A_WR_USED = 0;
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wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
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wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
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// wires for write data
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generate
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wire [19:0] A_write_data;
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wire [19:0] B_write_data;
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if (PORT_A_WIDTH == 16) begin
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assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
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assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
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assign A_write_data[9:8] = 2'b0;
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assign A_write_data[19:18] = 2'b0;
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end else begin
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assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
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end
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if (PORT_B_WIDTH == 16) begin
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assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
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assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
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assign B_write_data[9:8] = 2'b0;
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assign B_write_data[19:18] = 2'b0;
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end else begin
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assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
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end
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endgenerate
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// wires for read data
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wire [19:0] A_read_data;
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assign PORT_A_RD_DATA = A_read_data[PORT_A_WIDTH-1:0];
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wire [19:0] B_read_data;
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assign PORT_B_RD_DATA = B_read_data[PORT_B_WIDTH-1:0];
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// byte-write enables
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wire [1:0] A_write_EN = (PORT_A_WR_EN_WIDTH == 1) ? {1'b0, PORT_A_WR_EN} : PORT_A_WR_EN;
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wire [1:0] B_write_EN = (PORT_B_WR_EN_WIDTH == 1) ? {1'b0, PORT_B_WR_EN} : PORT_B_WR_EN;
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// port width
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wire [2:0] A_width = (PORT_A_WIDTH == 1) ? 3'b000 :
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(PORT_A_WIDTH == 2) ? 3'b001 :
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(PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
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(PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
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wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
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(PORT_B_WIDTH == 2) ? 3'b001 :
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(PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
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(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
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// write modes
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wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
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PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
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wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
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PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
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RAM1K20 #(
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`PARAMS_INIT_LSRAM
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) _TECHMAP_REPLACE_ (
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// port A
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.A_ADDR(A_address),
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.A_BLK_EN(A_BLK_SEL),
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.A_CLK(PORT_A_CLK),
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.A_DIN(A_write_data),
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.A_DOUT(A_read_data),
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.A_WEN(A_write_EN),
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.A_REN(PORT_A_RD_EN),
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.A_WIDTH(A_width),
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.A_WMODE(A_write_mode),
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.A_BYPASS(1'b1),
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.A_DOUT_EN(1'b1),
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.A_DOUT_SRST_N(1'b1),
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.A_DOUT_ARST_N(1'b1),
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// port B
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.B_ADDR(B_address),
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.B_BLK_EN(B_BLK_SEL),
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.B_CLK(PORT_B_CLK),
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.B_DIN(B_write_data),
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.B_DOUT(B_read_data),
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.B_WEN(B_write_EN),
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.B_REN(PORT_B_RD_EN),
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.B_WIDTH(B_width),
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.B_WMODE(B_write_mode),
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.B_BYPASS(1'b1),
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.B_DOUT_EN(1'b1),
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.B_DOUT_SRST_N(1'b1),
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.B_DOUT_ARST_N(1'b1),
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// Disable ECC for TDP
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.ECC_EN(1'b0),
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.ECC_BYPASS(1'b1),
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.BUSY_FB(1'b0)
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);
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endmodule
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// single dual port configuration
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module $__LSRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_WIDTH_CONFIG = "REGULAR";
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parameter ADDR_BITS = 14;
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parameter PORT_W_WIDTH = 1;
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parameter PORT_W_WR_EN_WIDTH = 4;
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parameter PORT_W_USED = 1;
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parameter PORT_R_WIDTH = 1;
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parameter PORT_R_USED = 0;
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input PORT_W_CLK;
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input [ADDR_BITS-1:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input PORT_R_CLK;
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input PORT_R_RD_EN;
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input [ADDR_BITS-1:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_R_RD_SRST;
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`include "brams_defs.vh"
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// address wires
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wire [ADDR_BITS-1:0] A_address;
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wire [ADDR_BITS-1:0] B_address;
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assign A_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_R_ADDR : {PORT_R_ADDR, 2'b00};
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assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_W_ADDR : {PORT_W_ADDR, 2'b00};
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// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
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// port A is for read, port B for write
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parameter PORT_W_USED = 0;
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parameter PORT_R_USED = 0;
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wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ? 3'b111 : 3'b000;
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wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ? 3'b111 : 3'b000;
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// read/write data & write enables
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// Currently support only wide write, width = {32, 40}
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generate
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wire [19:0] A_write_data;
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wire [19:0] B_write_data;
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wire [1:0] A_write_EN;
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wire [1:0] B_write_EN;
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// write port (A provides MSB)
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if (PORT_W_WIDTH == 32) begin
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assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
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assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
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assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
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assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
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assign B_write_data[4] = 1'b0;
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assign B_write_data[9] = 1'b0;
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assign B_write_data[14] = 1'b0;
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assign B_write_data[19] = 1'b0;
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assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
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assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
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assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
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assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
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assign A_write_data[4] = 1'b0;
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assign A_write_data[9] = 1'b0;
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assign A_write_data[14] = 1'b0;
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assign A_write_data[19] = 1'b0;
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end else if (PORT_W_WIDTH == 40) begin
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assign B_write_data = PORT_W_WR_DATA[19:0];
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assign A_write_data = PORT_W_WR_DATA[39:20];
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end
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// byte-write enables
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assign A_write_EN = PORT_W_WR_EN[1:0];
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assign B_write_EN = PORT_W_WR_EN[3:2];
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// read ports (A provides MSB)
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wire [19:0] A_read_data;
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wire [19:0] B_read_data;
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if (PORT_R_WIDTH == 32) begin
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assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
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assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
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assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
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assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
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assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
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assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
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assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
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assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
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end else if (PORT_R_WIDTH == 40) begin
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assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
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assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
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end
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endgenerate
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// port width
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wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
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(PORT_R_WIDTH == 2) ? 3'b001 :
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(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
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(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
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(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
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wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
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(PORT_W_WIDTH == 2) ? 3'b001 :
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(PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
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(PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
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(PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
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// write modes
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wire [1:0] A_write_mode = 2'b00;
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wire [1:0] B_write_mode = 2'b00;
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RAM1K20 #(
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`PARAMS_INIT_LSRAM
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) _TECHMAP_REPLACE_ (
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// port A - read
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.A_ADDR(A_address),
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.A_BLK_EN(A_BLK_SEL),
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.A_CLK(PORT_R_CLK),
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.A_DIN(A_write_data),
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.A_DOUT(A_read_data),
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.A_WEN(A_write_EN),
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.A_REN(PORT_R_RD_EN),
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.A_WIDTH(A_width),
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.A_WMODE(A_write_mode),
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.A_BYPASS(1'b1),
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.A_DOUT_EN(1'b1),
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.A_DOUT_SRST_N(1'b1),
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.A_DOUT_ARST_N(1'b1),
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// port B - write
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.B_ADDR(B_address),
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.B_BLK_EN(B_BLK_SEL),
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.B_CLK(PORT_W_CLK),
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.B_DIN(B_write_data),
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.B_DOUT(B_read_data),
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.B_WEN(B_write_EN),
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.B_REN(PORT_R_RD_EN),
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.B_WIDTH(B_width),
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.B_WMODE(B_write_mode),
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.B_BYPASS(1'b1),
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.B_DOUT_EN(1'b1),
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.B_DOUT_SRST_N(1'b1),
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.B_DOUT_ARST_N(1'b1),
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// Disable ECC for SDP
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.ECC_EN(1'b0),
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.ECC_BYPASS(1'b1),
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.BUSY_FB(1'b0)
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);
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endmodule
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