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yosys/techlibs
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Clifford Wolf ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
blackbox.sed initial import 2013-01-05 11:13:26 +01:00
simlib.v Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
stdcells.v Fixed shift ops with large right hand side 2013-07-09 18:59:59 +02:00
stdcells_sim.v initial import 2013-01-05 11:13:26 +01:00