mirror of https://github.com/YosysHQ/yosys.git
1080 lines
33 KiB
C++
1080 lines
33 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] The AIGER And-Inverter Graph (AIG) Format Version 20071012
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// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
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// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
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// https://stackoverflow.com/a/46137633
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#ifdef _MSC_VER
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#include <stdlib.h>
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#define __builtin_bswap32 _byteswap_ulong
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#elif defined(__APPLE__)
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#include <libkern/OSByteOrder.h>
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#define __builtin_bswap32 OSSwapInt32
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#endif
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#include <inttypes.h>
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "aigerparse.h"
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YOSYS_NAMESPACE_BEGIN
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inline int32_t from_big_endian(int32_t i32) {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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return __builtin_bswap32(i32);
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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return i32;
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#else
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#error "Unknown endianness"
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#endif
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}
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#define log_debug2(...) ;
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//#define log_debug2(...) log_debug(__VA_ARGS__)
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struct ConstEvalAig
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{
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RTLIL::Module *module;
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dict<RTLIL::SigBit, RTLIL::State> values_map;
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dict<RTLIL::SigBit, RTLIL::Cell*> sig2driver;
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dict<SigBit, pool<RTLIL::SigBit>> sig2deps;
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ConstEvalAig(RTLIL::Module *module) : module(module)
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{
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for (auto &it : module->cells_) {
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if (!yosys_celltypes.cell_known(it.second->type))
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continue;
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for (auto &it2 : it.second->connections())
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if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
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auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
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log_assert(r.second);
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}
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}
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}
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void clear()
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{
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values_map.clear();
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sig2deps.clear();
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}
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void set(RTLIL::SigBit sig, RTLIL::State value)
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{
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auto it = values_map.find(sig);
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#ifndef NDEBUG
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if (it != values_map.end()) {
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RTLIL::State current_val = it->second;
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log_assert(current_val == value);
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}
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#endif
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if (it != values_map.end())
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it->second = value;
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else
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values_map[sig] = value;
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}
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void set_incremental(RTLIL::SigSpec sig, RTLIL::Const value)
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{
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log_assert(GetSize(sig) == GetSize(value));
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for (int i = 0; i < GetSize(sig); i++) {
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auto it = values_map.find(sig[i]);
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if (it != values_map.end()) {
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RTLIL::State current_val = it->second;
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if (current_val != value[i])
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for (auto dep : sig2deps[sig[i]])
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values_map.erase(dep);
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it->second = value[i];
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}
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else
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values_map[sig[i]] = value[i];
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}
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}
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void compute_deps(RTLIL::SigBit output, const pool<RTLIL::SigBit> &inputs)
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{
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sig2deps[output].insert(output);
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RTLIL::Cell *cell = sig2driver.at(output);
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_a))
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compute_deps(sig_a, inputs);
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_b))
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compute_deps(sig_b, inputs);
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}
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else if (cell->type == "$_NOT_") {
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}
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else log_abort();
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}
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bool eval(RTLIL::Cell *cell)
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{
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RTLIL::SigBit sig_y = cell->getPort("\\Y");
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if (values_map.count(sig_y))
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return true;
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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if (!eval(sig_a))
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return false;
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RTLIL::State eval_ret = RTLIL::Sx;
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if (cell->type == "$_NOT_") {
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if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
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else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
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}
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else if (cell->type == "$_AND_") {
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if (sig_a == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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{
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RTLIL::SigBit sig_b = cell->getPort("\\B");
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if (!eval(sig_b))
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return false;
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if (sig_b == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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if (sig_a != RTLIL::S1 || sig_b != RTLIL::S1)
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goto eval_end;
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eval_ret = RTLIL::S1;
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}
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}
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else log_abort();
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eval_end:
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set(sig_y, eval_ret);
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return true;
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}
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bool eval(RTLIL::SigBit &sig)
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{
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auto it = values_map.find(sig);
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if (it != values_map.end()) {
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sig = it->second;
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return true;
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}
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RTLIL::Cell *cell = sig2driver.at(sig);
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if (!eval(cell))
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return false;
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it = values_map.find(sig);
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if (it != values_map.end()) {
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sig = it->second;
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return true;
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}
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return false;
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}
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};
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
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: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
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{
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module = new RTLIL::Module;
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module->name = module_name;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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}
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void AigerReader::parse_aiger()
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{
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std::string header;
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f >> header;
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if (header != "aag" && header != "aig")
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log_error("Unsupported AIGER file!\n");
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// Parse rest of header
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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// Optional values
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B = C = J = F = 0;
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> B)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> C)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> J)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> F)) log_error("Invalid AIGER header\n");
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end_of_header:
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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line_count = 1;
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piNum = 0;
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flopNum = 0;
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if (header == "aag")
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary();
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else
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log_abort();
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RTLIL::Wire* n0 = module->wire("\\__0__");
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if (n0)
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module->connect(n0, RTLIL::S0);
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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std::string s;
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
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f.ignore(1);
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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log_error("Line %u has invalid symbol position!\n", line_count);
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RTLIL::Wire* wire;
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if (c == 'i') wire = inputs[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'o') wire = outputs[l1];
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else if (c == 'b') wire = bad_properties[l1];
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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else if (c == 'j' || c == 'f') {
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// TODO
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}
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else if (c == 'c') {
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f.ignore(1);
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if (f.peek() == '\n')
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break;
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// Else constraint (TODO)
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}
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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}
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post_process();
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}
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static uint32_t parse_xaiger_literal(std::istream &f)
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{
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uint32_t l;
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f.read(reinterpret_cast<char*>(&l), sizeof(l));
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if (f.gcount() != sizeof(l))
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log_error("Offset %" PRId64 ": unable to read literal!\n", static_cast<int64_t>(f.tellg()));
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return from_big_endian(l);
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}
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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{
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : ""));
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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log_debug2("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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wire->port_input = wire->port_output = false;
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable));
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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if (wire_inv) {
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if (module->cell(wire_inv_name)) return wire;
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}
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else {
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log_debug2("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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wire_inv->port_input = wire_inv->port_output = false;
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}
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log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire);
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return wire;
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}
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void AigerReader::parse_xaiger()
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{
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std::string header;
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f >> header;
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if (header != "aag" && header != "aig")
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log_error("Unsupported AIGER file!\n");
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// Parse rest of header
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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// Optional values
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B = C = J = F = 0;
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
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line_count = 1;
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piNum = 0;
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flopNum = 0;
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if (header == "aag")
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary();
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else
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log_abort();
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RTLIL::Wire* n0 = module->wire("\\__0__");
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if (n0)
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module->connect(n0, RTLIL::S0);
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dict<int,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find("\\abc_box_id");
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(id, m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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}
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// Parse footer (symbol table, comments, etc.)
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std::string s;
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bool comment_seen = false;
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for (int c = f.peek(); c != EOF; c = f.peek()) {
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if (comment_seen || c == 'c') {
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if (!comment_seen) {
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f.ignore(1);
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c = f.peek();
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comment_seen = true;
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}
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if (c == '\n')
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break;
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f.ignore(1);
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize = parse_xaiger_literal(f);
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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ConstEvalAig ce(module);
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug2("\t%u\n", nodeID);
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RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
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log_assert(wire);
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input_sig.append(wire);
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}
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
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RTLIL::SigBit o(output_sig);
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bool success = ce.eval(o);
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log_assert(success);
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log_assert(o.wire == nullptr);
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lut_mask[gray] = o.data;
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}
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RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
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log_assert(output_cell);
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module->remove(output_cell);
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module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
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}
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}
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else if (c == 'r') {
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uint32_t dataSize = parse_xaiger_literal(f);
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flopNum = parse_xaiger_literal(f);
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log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
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f.ignore(flopNum * sizeof(uint32_t));
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}
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else if (c == 'n') {
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parse_xaiger_literal(f);
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f >> s;
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log_debug("n: '%s'\n", s.c_str());
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}
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else if (c == 'h') {
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f.ignore(sizeof(uint32_t));
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uint32_t version = parse_xaiger_literal(f);
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log_assert(version == 1);
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uint32_t ciNum = parse_xaiger_literal(f);
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log_debug("ciNum = %u\n", ciNum);
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uint32_t coNum = parse_xaiger_literal(f);
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log_debug("coNum = %u\n", coNum);
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piNum = parse_xaiger_literal(f);
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log_debug("piNum = %u\n", piNum);
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uint32_t poNum = parse_xaiger_literal(f);
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log_debug("poNum = %u\n", poNum);
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uint32_t boxNum = parse_xaiger_literal(f);
|
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log_debug("boxNum = %u\n", poNum);
|
|
for (unsigned i = 0; i < boxNum; i++) {
|
|
f.ignore(2*sizeof(uint32_t));
|
|
uint32_t boxUniqueId = parse_xaiger_literal(f);
|
|
log_assert(boxUniqueId > 0);
|
|
uint32_t oldBoxNum = parse_xaiger_literal(f);
|
|
RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
|
|
boxes.emplace_back(cell);
|
|
}
|
|
}
|
|
else if (c == 'a' || c == 'i' || c == 'o') {
|
|
uint32_t dataSize = parse_xaiger_literal(f);
|
|
f.ignore(dataSize);
|
|
}
|
|
else {
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
|
|
}
|
|
|
|
post_process();
|
|
}
|
|
|
|
void AigerReader::parse_aiger_ascii()
|
|
{
|
|
std::string line;
|
|
std::stringstream ss;
|
|
|
|
unsigned l1, l2, l3;
|
|
|
|
// Parse inputs
|
|
for (unsigned i = 1; i <= I; ++i, ++line_count) {
|
|
if (!(f >> l1))
|
|
log_error("Line %u cannot be interpreted as an input!\n", line_count);
|
|
log_debug2("%d is an input\n", l1);
|
|
log_assert(!(l1 & 1)); // Inputs can't be inverted
|
|
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
|
wire->port_input = true;
|
|
inputs.push_back(wire);
|
|
}
|
|
|
|
// Parse latches
|
|
RTLIL::Wire *clk_wire = nullptr;
|
|
if (L > 0) {
|
|
log_assert(clk_name != "");
|
|
clk_wire = module->wire(clk_name);
|
|
log_assert(!clk_wire);
|
|
log_debug2("Creating %s\n", clk_name.c_str());
|
|
clk_wire = module->addWire(clk_name);
|
|
clk_wire->port_input = true;
|
|
clk_wire->port_output = false;
|
|
}
|
|
for (unsigned i = 0; i < L; ++i, ++line_count) {
|
|
if (!(f >> l1 >> l2))
|
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
|
log_debug2("%d %d is a latch\n", l1, l2);
|
|
log_assert(!(l1 & 1));
|
|
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
|
|
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
|
|
|
|
module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
|
|
|
|
// Reset logic is optional in AIGER 1.9
|
|
if (f.peek() == ' ') {
|
|
if (!(f >> l3))
|
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
|
|
|
if (l3 == 0)
|
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
|
else if (l3 == 1)
|
|
q_wire->attributes["\\init"] = RTLIL::S1;
|
|
else if (l3 == l1) {
|
|
//q_wire->attributes["\\init"] = RTLIL::Sx;
|
|
}
|
|
else
|
|
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
|
}
|
|
else {
|
|
// AIGER latches are assumed to be initialized to zero
|
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
|
}
|
|
latches.push_back(q_wire);
|
|
}
|
|
|
|
// Parse outputs
|
|
for (unsigned i = 0; i < O; ++i, ++line_count) {
|
|
if (!(f >> l1))
|
|
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
|
|
|
log_debug2("%d is an output\n", l1);
|
|
const unsigned variable = l1 >> 1;
|
|
const bool invert = l1 & 1;
|
|
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
|
|
RTLIL::Wire *wire = module->wire(wire_name);
|
|
if (!wire)
|
|
wire = createWireIfNotExists(module, l1);
|
|
else if (wire->port_input || wire->port_output) {
|
|
RTLIL::Wire *new_wire = module->addWire(NEW_ID);
|
|
module->connect(new_wire, wire);
|
|
wire = new_wire;
|
|
}
|
|
wire->port_output = true;
|
|
outputs.push_back(wire);
|
|
}
|
|
|
|
// Parse bad properties
|
|
for (unsigned i = 0; i < B; ++i, ++line_count) {
|
|
if (!(f >> l1))
|
|
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
|
|
|
log_debug2("%d is a bad state property\n", l1);
|
|
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
|
wire->port_output = true;
|
|
bad_properties.push_back(wire);
|
|
}
|
|
|
|
// TODO: Parse invariant constraints
|
|
for (unsigned i = 0; i < C; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// TODO: Parse justice properties
|
|
for (unsigned i = 0; i < J; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// TODO: Parse fairness constraints
|
|
for (unsigned i = 0; i < F; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// Parse AND
|
|
for (unsigned i = 0; i < A; ++i) {
|
|
if (!(f >> l1 >> l2 >> l3))
|
|
log_error("Line %u cannot be interpreted as an AND!\n", line_count);
|
|
|
|
log_debug2("%d %d %d is an AND\n", l1, l2, l3);
|
|
log_assert(!(l1 & 1));
|
|
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
|
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
|
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
|
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
|
|
}
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
}
|
|
|
|
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
|
|
{
|
|
unsigned x = 0, i = 0;
|
|
unsigned char ch;
|
|
while ((ch = f.get()) & 0x80)
|
|
x |= (ch & 0x7f) << (7 * i++);
|
|
return ref - (x | (ch << (7 * i)));
|
|
}
|
|
|
|
void AigerReader::parse_aiger_binary()
|
|
{
|
|
unsigned l1, l2, l3;
|
|
std::string line;
|
|
|
|
// Parse inputs
|
|
for (unsigned i = 1; i <= I; ++i) {
|
|
log_debug2("%d is an input\n", i);
|
|
RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
|
|
wire->port_input = true;
|
|
log_assert(!wire->port_output);
|
|
inputs.push_back(wire);
|
|
}
|
|
|
|
// Parse latches
|
|
RTLIL::Wire *clk_wire = nullptr;
|
|
if (L > 0) {
|
|
log_assert(clk_name != "");
|
|
clk_wire = module->wire(clk_name);
|
|
log_assert(!clk_wire);
|
|
log_debug2("Creating %s\n", clk_name.c_str());
|
|
clk_wire = module->addWire(clk_name);
|
|
clk_wire->port_input = true;
|
|
clk_wire->port_output = false;
|
|
}
|
|
l1 = (I+1) * 2;
|
|
for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
|
|
if (!(f >> l2))
|
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
|
log_debug("%d %d is a latch\n", l1, l2);
|
|
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
|
|
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
|
|
|
|
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
|
|
|
|
// Reset logic is optional in AIGER 1.9
|
|
if (f.peek() == ' ') {
|
|
if (!(f >> l3))
|
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
|
|
|
if (l3 == 0)
|
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
|
else if (l3 == 1)
|
|
q_wire->attributes["\\init"] = RTLIL::S1;
|
|
else if (l3 == l1) {
|
|
//q_wire->attributes["\\init"] = RTLIL::Sx;
|
|
}
|
|
else
|
|
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
|
}
|
|
else {
|
|
// AIGER latches are assumed to be initialized to zero
|
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
|
}
|
|
latches.push_back(q_wire);
|
|
}
|
|
|
|
// Parse outputs
|
|
for (unsigned i = 0; i < O; ++i, ++line_count) {
|
|
if (!(f >> l1))
|
|
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
|
|
|
log_debug2("%d is an output\n", l1);
|
|
const unsigned variable = l1 >> 1;
|
|
const bool invert = l1 & 1;
|
|
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
|
|
RTLIL::Wire *wire = module->wire(wire_name);
|
|
if (!wire)
|
|
wire = createWireIfNotExists(module, l1);
|
|
else if (wire->port_input || wire->port_output) {
|
|
RTLIL::Wire *new_wire = module->addWire(NEW_ID);
|
|
module->connect(new_wire, wire);
|
|
wire = new_wire;
|
|
}
|
|
wire->port_output = true;
|
|
outputs.push_back(wire);
|
|
}
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// Parse bad properties
|
|
for (unsigned i = 0; i < B; ++i, ++line_count) {
|
|
if (!(f >> l1))
|
|
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
|
|
|
log_debug2("%d is a bad state property\n", l1);
|
|
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
|
wire->port_output = true;
|
|
bad_properties.push_back(wire);
|
|
}
|
|
if (B > 0)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// TODO: Parse invariant constraints
|
|
for (unsigned i = 0; i < C; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// TODO: Parse justice properties
|
|
for (unsigned i = 0; i < J; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// TODO: Parse fairness constraints
|
|
for (unsigned i = 0; i < F; ++i, ++line_count)
|
|
std::getline(f, line); // Ignore up to start of next line
|
|
|
|
// Parse AND
|
|
l1 = (I+L+1) << 1;
|
|
for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
|
|
l2 = parse_next_delta_literal(f, l1);
|
|
l3 = parse_next_delta_literal(f, l2);
|
|
|
|
log_debug2("%d %d %d is an AND\n", l1, l2, l3);
|
|
log_assert(!(l1 & 1));
|
|
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
|
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
|
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
|
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
|
|
}
|
|
}
|
|
|
|
void AigerReader::post_process()
|
|
{
|
|
pool<IdString> seen_boxes;
|
|
unsigned ci_count = 0, co_count = 0;
|
|
for (auto cell : boxes) {
|
|
RTLIL::Module* box_module = design->module(cell->type);
|
|
log_assert(box_module);
|
|
|
|
if (seen_boxes.insert(cell->type).second) {
|
|
auto it = box_module->attributes.find("\\abc_carry");
|
|
if (it != box_module->attributes.end()) {
|
|
RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
|
|
auto carry_in_out = it->second.decode_string();
|
|
auto pos = carry_in_out.find(',');
|
|
if (pos == std::string::npos)
|
|
log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
|
|
auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
|
|
carry_in = box_module->wire(carry_in_name);
|
|
if (!carry_in || !carry_in->port_input)
|
|
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
|
|
|
|
auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
|
|
carry_out = box_module->wire(carry_out_name);
|
|
if (!carry_out || !carry_out->port_output)
|
|
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
|
|
|
|
auto &ports = box_module->ports;
|
|
for (auto jt = ports.begin(); jt != ports.end(); ) {
|
|
RTLIL::Wire* w = box_module->wire(*jt);
|
|
log_assert(w);
|
|
if (w == carry_in || w == carry_out) {
|
|
jt = ports.erase(jt);
|
|
continue;
|
|
}
|
|
if (w->port_id > carry_in->port_id)
|
|
--w->port_id;
|
|
if (w->port_id > carry_out->port_id)
|
|
--w->port_id;
|
|
log_assert(w->port_input || w->port_output);
|
|
log_assert(ports[w->port_id-1] == w->name);
|
|
++jt;
|
|
}
|
|
ports.push_back(carry_in->name);
|
|
carry_in->port_id = ports.size();
|
|
ports.push_back(carry_out->name);
|
|
carry_out->port_id = ports.size();
|
|
}
|
|
}
|
|
|
|
// NB: Assume box_module->ports are sorted alphabetically
|
|
// (as RTLIL::Module::fixup_ports() would do)
|
|
for (auto port_name : box_module->ports) {
|
|
RTLIL::Wire* w = box_module->wire(port_name);
|
|
log_assert(w);
|
|
RTLIL::SigSpec rhs;
|
|
RTLIL::Wire* wire = nullptr;
|
|
for (int i = 0; i < GetSize(w); i++) {
|
|
if (w->port_input) {
|
|
log_assert(co_count < outputs.size());
|
|
wire = outputs[co_count++];
|
|
log_assert(wire);
|
|
log_assert(wire->port_output);
|
|
wire->port_output = false;
|
|
}
|
|
if (w->port_output) {
|
|
log_assert((piNum + ci_count) < inputs.size());
|
|
wire = inputs[piNum + ci_count++];
|
|
log_assert(wire);
|
|
log_assert(wire->port_input);
|
|
wire->port_input = false;
|
|
}
|
|
rhs.append(wire);
|
|
}
|
|
cell->setPort(port_name, rhs);
|
|
}
|
|
}
|
|
|
|
dict<RTLIL::IdString, int> wideports_cache;
|
|
|
|
if (!map_filename.empty()) {
|
|
std::ifstream mf(map_filename);
|
|
std::string type, symbol;
|
|
int variable, index;
|
|
while (mf >> type >> variable >> index >> symbol) {
|
|
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
|
|
if (type == "input") {
|
|
log_assert(static_cast<unsigned>(variable) < inputs.size());
|
|
RTLIL::Wire* wire = inputs[variable];
|
|
log_assert(wire);
|
|
log_assert(wire->port_input);
|
|
|
|
if (index == 0) {
|
|
// Cope with the fact that a CI might be identical
|
|
// to a PI (necessary due to ABC); in those cases
|
|
// simply connect the latter to the former
|
|
RTLIL::Wire* existing = module->wire(escaped_s);
|
|
if (!existing)
|
|
module->rename(wire, escaped_s);
|
|
else {
|
|
wire->port_input = false;
|
|
module->connect(wire, existing);
|
|
}
|
|
}
|
|
else if (index > 0) {
|
|
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
|
|
RTLIL::Wire* existing = module->wire(indexed_name);
|
|
if (!existing) {
|
|
module->rename(wire, indexed_name);
|
|
if (wideports)
|
|
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
|
}
|
|
else {
|
|
module->connect(wire, existing);
|
|
wire->port_input = false;
|
|
}
|
|
}
|
|
}
|
|
else if (type == "output") {
|
|
log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
|
|
RTLIL::Wire* wire = outputs[variable + co_count];
|
|
log_assert(wire);
|
|
log_assert(wire->port_output);
|
|
if (escaped_s == "$__dummy__") {
|
|
wire->port_output = false;
|
|
continue;
|
|
}
|
|
|
|
if (index == 0) {
|
|
// Cope with the fact that a CO might be identical
|
|
// to a PO (necessary due to ABC); in those cases
|
|
// simply connect the latter to the former
|
|
RTLIL::Wire* existing = module->wire(escaped_s);
|
|
if (!existing) {
|
|
if (escaped_s.ends_with("$inout.out")) {
|
|
wire->port_output = false;
|
|
RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
|
|
log_assert(in_wire);
|
|
log_assert(in_wire->port_input && !in_wire->port_output);
|
|
in_wire->port_output = true;
|
|
module->connect(in_wire, wire);
|
|
}
|
|
else
|
|
module->rename(wire, escaped_s);
|
|
}
|
|
else {
|
|
wire->port_output = false;
|
|
module->connect(wire, existing);
|
|
}
|
|
}
|
|
else if (index > 0) {
|
|
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
|
|
RTLIL::Wire* existing = module->wire(indexed_name);
|
|
if (!existing) {
|
|
if (escaped_s.ends_with("$inout.out")) {
|
|
wire->port_output = false;
|
|
RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
|
|
log_assert(in_wire);
|
|
log_assert(in_wire->port_input && !in_wire->port_output);
|
|
in_wire->port_output = true;
|
|
module->connect(in_wire, wire);
|
|
}
|
|
else {
|
|
module->rename(wire, indexed_name);
|
|
if (wideports)
|
|
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
|
}
|
|
}
|
|
else {
|
|
module->connect(wire, existing);
|
|
wire->port_output = false;
|
|
}
|
|
}
|
|
}
|
|
else if (type == "box") {
|
|
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
|
|
if (cell) { // ABC could have optimised this box away
|
|
module->rename(cell, escaped_s);
|
|
RTLIL::Module* box_module = design->module(cell->type);
|
|
log_assert(box_module);
|
|
|
|
for (const auto &i : cell->connections()) {
|
|
RTLIL::IdString port_name = i.first;
|
|
RTLIL::SigSpec rhs = i.second;
|
|
int index = 0;
|
|
for (auto bit : rhs.bits()) {
|
|
RTLIL::Wire* wire = bit.wire;
|
|
RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
|
|
if (index == 0)
|
|
module->rename(wire, escaped_s);
|
|
else if (index > 0) {
|
|
module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
|
|
if (wideports)
|
|
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
|
}
|
|
index++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
log_error("Symbol type '%s' not recognised.\n", type.c_str());
|
|
}
|
|
}
|
|
|
|
for (auto &wp : wideports_cache) {
|
|
auto name = wp.first;
|
|
int width = wp.second + 1;
|
|
|
|
RTLIL::Wire *wire = module->wire(name);
|
|
if (wire)
|
|
module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
|
|
|
|
// Do not make ports with a mix of input/output into
|
|
// wide ports
|
|
bool port_input = false, port_output = false;
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
|
|
RTLIL::Wire *other_wire = module->wire(other_name);
|
|
if (other_wire) {
|
|
port_input = port_input || other_wire->port_input;
|
|
port_output = port_output || other_wire->port_output;
|
|
}
|
|
}
|
|
|
|
wire = module->addWire(name, width);
|
|
wire->port_input = port_input;
|
|
wire->port_output = port_output;
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
|
|
RTLIL::Wire *other_wire = module->wire(other_name);
|
|
if (other_wire) {
|
|
other_wire->port_input = false;
|
|
other_wire->port_output = false;
|
|
}
|
|
if (wire->port_input) {
|
|
if (other_wire)
|
|
module->connect(other_wire, SigSpec(wire, i));
|
|
}
|
|
else {
|
|
// Since we skip POs that are connected to Sx,
|
|
// re-connect them here
|
|
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
|
|
}
|
|
}
|
|
}
|
|
|
|
module->fixup_ports();
|
|
design->add(module);
|
|
|
|
design->selection_stack.emplace_back(false);
|
|
RTLIL::Selection& sel = design->selection_stack.back();
|
|
sel.select(module);
|
|
|
|
Pass::call(design, "clean");
|
|
|
|
design->selection_stack.pop_back();
|
|
|
|
for (auto cell : module->cells().to_vector()) {
|
|
if (cell->type != "$lut") continue;
|
|
auto y_port = cell->getPort("\\Y").as_bit();
|
|
if (y_port.wire->width == 1)
|
|
module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
|
|
else
|
|
module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
|
|
}
|
|
}
|
|
|
|
struct AigerFrontend : public Frontend {
|
|
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" read_aiger [options] [filename]\n");
|
|
log("\n");
|
|
log("Load module from an AIGER file into the current design.\n");
|
|
log("\n");
|
|
log(" -module_name <module_name>\n");
|
|
log(" Name of module to be created (default: <filename>)\n");
|
|
log("\n");
|
|
log(" -clk_name <wire_name>\n");
|
|
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
|
|
log(" this name (default: clk)\n");
|
|
log("\n");
|
|
log(" -map <filename>\n");
|
|
log(" read file with port and latch symbols\n");
|
|
log("\n");
|
|
log(" -wideports\n");
|
|
log(" Merge ports that match the pattern 'name[int]' into a single\n");
|
|
log(" multi-bit port 'name'.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
log_header(design, "Executing AIGER frontend.\n");
|
|
|
|
RTLIL::IdString clk_name = "\\clk";
|
|
RTLIL::IdString module_name;
|
|
std::string map_filename;
|
|
bool wideports = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-module_name" && argidx+1 < args.size()) {
|
|
module_name = RTLIL::escape_id(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (arg == "-clk_name" && argidx+1 < args.size()) {
|
|
clk_name = RTLIL::escape_id(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
|
|
map_filename = args[++argidx];
|
|
continue;
|
|
}
|
|
if (arg == "-wideports") {
|
|
wideports = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
if (module_name.empty()) {
|
|
#ifdef _WIN32
|
|
char fname[_MAX_FNAME];
|
|
_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
|
|
module_name = fname;
|
|
#else
|
|
char* bn = strdup(filename.c_str());
|
|
module_name = RTLIL::escape_id(bn);
|
|
free(bn);
|
|
#endif
|
|
}
|
|
|
|
AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
|
|
reader.parse_aiger();
|
|
}
|
|
} AigerFrontend;
|
|
|
|
YOSYS_NAMESPACE_END
|