mirror of https://github.com/YosysHQ/yosys.git
27 lines
771 B
Verilog
27 lines
771 B
Verilog
// This file exists to map purely-synchronous flops to ABC9 flops, while
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// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
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// doesn't support asynchronous-set/clear flops in sequential synthesis.
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module dffepc (
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output Q,
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input D,
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input CLK,
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input EN,
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input CLR,
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input PRE
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);
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parameter INIT = 1'b0;
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parameter _TECHMAP_CONSTMSK_CLR_ = 1'b0;
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parameter _TECHMAP_CONSTMSK_PRE_ = 1'b0;
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parameter _TECHMAP_CONSTVAL_CLR_ = 1'b0;
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parameter _TECHMAP_CONSTVAL_PRE_ = 1'b0;
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if (_TECHMAP_CONSTMSK_CLR_ != 1'b0 && _TECHMAP_CONSTMSK_PRE_ != 1'b0 && _TECHMAP_CONSTVAL_CLR_ == 1'b0 && _TECHMAP_CONSTVAL_PRE_ == 1'b0)
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$__PP3_DFFEPC_SYNCONLY _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN));
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else
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wire _TECHMAP_FAIL_ = 1;
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endmodule
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