yosys/frontends/verilog
N. Engelhardt d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add one mode dependency 2020-03-19 16:53:40 +01:00
const2ast.cc Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
preproc.cc Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Merge pull request #1811 from PeterCrozier/typedef_scope 2020-03-30 13:55:39 +02:00
verilog_frontend.h Merge pull request #1811 from PeterCrozier/typedef_scope 2020-03-30 13:55:39 +02:00
verilog_lexer.l Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
verilog_parser.y Inline productions to follow house style. 2020-03-27 16:21:45 +00:00