mirror of https://github.com/YosysHQ/yosys.git
70 lines
1.1 KiB
Plaintext
70 lines
1.1 KiB
Plaintext
ram block $__ANLOGIC_BRAM_TDP_ {
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abits 13;
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widths 1 2 4 9 per_port;
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cost 64;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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portoption "WRITEMODE" "READBEFOREWRITE" {
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rdwr old;
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}
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated block_wr;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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}
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ram block $__ANLOGIC_BRAM_SDP_ {
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abits 13;
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widths 1 2 4 9 18 per_port;
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byte 9;
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cost 64;
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init no_undef;
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port sr "R" {
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clock anyedge;
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clken;
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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port sw "W" {
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clock anyedge;
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clken;
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}
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}
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ram block $__ANLOGIC_BRAM32K_ {
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abits 12;
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widths 8 16 per_port;
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byte 8;
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cost 192;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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# no reset - it doesn't really work without the pipeline
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# output registers
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}
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}
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