mirror of https://github.com/YosysHQ/yosys.git
8c05f14b58
Although the current style is allowed by the standard, Icarus verilog
doesn't parse default assignments using an implicit net type:
techlibs/ice40/cells_sim.v:305: syntax error
techlibs/ice40/cells_sim.v:1: Errors in port declarations.
Fix this by making sure that ports with default assignments first on
their line.
Fixes:
|
||
|---|---|---|
| .. | ||
| tests | ||
| Makefile.inc | ||
| abc9_model.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| dsp_map.v | ||
| ff_map.v | ||
| ice40_braminit.cc | ||
| ice40_opt.cc | ||
| latches_map.v | ||
| spram.txt | ||
| spram_map.v | ||
| synth_ice40.cc | ||