This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
0cd68f15cf
yosys
/
tests
/
various
/
abc9.v
6 lines
86 B
Verilog
Raw
Blame
History
module
abc9_test027
(
output
reg
o
)
;
initial
o
=
1
'b0
;
always
@
*
o
<
=
~
o
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink