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yosys/techlibs
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Clifford Wolf 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
..
common Progress in cell library documentation 2016-02-01 13:58:10 +01:00
greenpak4 Added nlutmap 2015-09-18 21:57:34 +02:00
ice40 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
xilinx Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00