yosys/frontends/verilog
Alberto Gonzalez 6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
const2ast.cc Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
preproc.cc Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
verilog_frontend.cc Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
verilog_frontend.h Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
verilog_lexer.l refixed parsing of constant with comment between size and value 2020-03-11 18:21:44 +01:00
verilog_parser.y Add AST node source location information in a couple more parser rules. 2020-03-17 06:22:12 +00:00