mirror of https://github.com/YosysHQ/yosys.git
508 lines
17 KiB
C++
508 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CELLTYPES_H
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#define CELLTYPES_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct CellType
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{
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RTLIL::IdString type;
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pool<RTLIL::IdString> inputs, outputs;
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bool is_evaluable;
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};
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struct CellTypes
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{
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dict<RTLIL::IdString, CellType> cell_types;
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CellTypes()
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{
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}
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CellTypes(RTLIL::Design *design)
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{
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setup(design);
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}
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void setup(RTLIL::Design *design = NULL)
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{
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if (design)
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setup_design(design);
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setup_internals();
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setup_internals_mem();
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setup_stdcells();
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setup_stdcells_mem();
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}
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void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
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{
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CellType ct = {type, inputs, outputs, is_evaluable};
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cell_types[ct.type] = ct;
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}
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void setup_module(RTLIL::Module *module)
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{
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pool<RTLIL::IdString> inputs, outputs;
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for (RTLIL::IdString wire_name : module->ports) {
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire->port_input)
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inputs.insert(wire->name);
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if (wire->port_output)
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outputs.insert(wire->name);
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}
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setup_type(module->name, inputs, outputs);
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}
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void setup_design(RTLIL::Design *design)
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{
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for (auto module : design->modules())
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setup_module(module);
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}
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void setup_internals()
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{
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setup_internals_eval();
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setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
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setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
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setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
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setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
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setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
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setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
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setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
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setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
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setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
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setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
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setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
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setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
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setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
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setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
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}
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void setup_internals_eval()
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{
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std::vector<RTLIL::IdString> unary_ops = {
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ID($not), ID($pos), ID($neg),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
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ID($logic_not), ID($slice), ID($lut), ID($sop)
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};
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std::vector<RTLIL::IdString> binary_ops = {
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ID($and), ID($or), ID($xor), ID($xnor),
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ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
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ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
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ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
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ID($logic_and), ID($logic_or), ID($concat), ID($macc)
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};
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for (auto type : unary_ops)
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setup_type(type, {ID::A}, {ID::Y}, true);
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for (auto type : binary_ops)
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setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
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for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
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setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
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setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
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setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
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setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
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}
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void setup_internals_ff()
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{
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setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
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setup_type(ID($ff), {ID::D}, {ID::Q});
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setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
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setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
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setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
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setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::E}, {ID::Q});
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setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
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setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::E}, {ID::Q});
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setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
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setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
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setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
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setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
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setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
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setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
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}
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void setup_internals_mem()
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{
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setup_internals_ff();
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setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
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setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
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setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
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setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
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setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
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}
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void setup_stdcells()
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{
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setup_stdcells_eval();
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setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
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}
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void setup_stdcells_eval()
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{
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setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
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setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
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setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
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setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
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setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
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setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
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setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
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setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
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setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
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setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
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setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
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setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
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}
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void setup_stdcells_mem()
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{
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std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
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setup_type(ID($_FF_), {ID::D}, {ID::Q});
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for (auto c1 : list_np)
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setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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for (auto c4 : list_np)
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setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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for (auto c4 : list_np)
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setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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for (auto c4 : list_np)
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setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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for (auto c4 : list_np)
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setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
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for (auto c1 : list_np)
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setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
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}
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void clear()
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{
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cell_types.clear();
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}
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bool cell_known(RTLIL::IdString type) const
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{
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return cell_types.count(type) != 0;
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}
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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}
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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}
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bool cell_evaluable(RTLIL::IdString type) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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}
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static RTLIL::Const eval_not(RTLIL::Const v)
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{
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for (auto &bit : v.bits)
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if (bit == State::S0) bit = State::S1;
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else if (bit == State::S1) bit = State::S0;
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return v;
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}
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static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
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{
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if (type == ID($sshr) && !signed1)
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type = ID($shr);
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if (type == ID($sshl) && !signed1)
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type = ID($shl);
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if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
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type != ID($pos) && type != ID($neg) && type != ID($not)) {
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if (!signed1 || !signed2)
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signed1 = false, signed2 = false;
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}
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#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
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HANDLE_CELL_TYPE(not)
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HANDLE_CELL_TYPE(and)
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HANDLE_CELL_TYPE(or)
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HANDLE_CELL_TYPE(xor)
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HANDLE_CELL_TYPE(xnor)
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HANDLE_CELL_TYPE(reduce_and)
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HANDLE_CELL_TYPE(reduce_or)
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HANDLE_CELL_TYPE(reduce_xor)
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HANDLE_CELL_TYPE(reduce_xnor)
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HANDLE_CELL_TYPE(reduce_bool)
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HANDLE_CELL_TYPE(logic_not)
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HANDLE_CELL_TYPE(logic_and)
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HANDLE_CELL_TYPE(logic_or)
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HANDLE_CELL_TYPE(shl)
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HANDLE_CELL_TYPE(shr)
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HANDLE_CELL_TYPE(sshl)
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HANDLE_CELL_TYPE(sshr)
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HANDLE_CELL_TYPE(shift)
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HANDLE_CELL_TYPE(shiftx)
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HANDLE_CELL_TYPE(lt)
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HANDLE_CELL_TYPE(le)
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HANDLE_CELL_TYPE(eq)
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HANDLE_CELL_TYPE(ne)
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HANDLE_CELL_TYPE(eqx)
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HANDLE_CELL_TYPE(nex)
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HANDLE_CELL_TYPE(ge)
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HANDLE_CELL_TYPE(gt)
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HANDLE_CELL_TYPE(add)
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HANDLE_CELL_TYPE(sub)
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HANDLE_CELL_TYPE(mul)
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HANDLE_CELL_TYPE(div)
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HANDLE_CELL_TYPE(mod)
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HANDLE_CELL_TYPE(divfloor)
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HANDLE_CELL_TYPE(modfloor)
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HANDLE_CELL_TYPE(pow)
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HANDLE_CELL_TYPE(pos)
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HANDLE_CELL_TYPE(neg)
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#undef HANDLE_CELL_TYPE
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if (type == ID($_BUF_))
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return arg1;
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if (type == ID($_NOT_))
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return eval_not(arg1);
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if (type == ID($_AND_))
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return const_and(arg1, arg2, false, false, 1);
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if (type == ID($_NAND_))
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return eval_not(const_and(arg1, arg2, false, false, 1));
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if (type == ID($_OR_))
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return const_or(arg1, arg2, false, false, 1);
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if (type == ID($_NOR_))
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return eval_not(const_or(arg1, arg2, false, false, 1));
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if (type == ID($_XOR_))
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return const_xor(arg1, arg2, false, false, 1);
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if (type == ID($_XNOR_))
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return const_xnor(arg1, arg2, false, false, 1);
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if (type == ID($_ANDNOT_))
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return const_and(arg1, eval_not(arg2), false, false, 1);
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if (type == ID($_ORNOT_))
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return const_or(arg1, eval_not(arg2), false, false, 1);
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if (errp != nullptr) {
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*errp = true;
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return State::Sm;
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}
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log_abort();
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
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{
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if (cell->type == ID($slice)) {
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RTLIL::Const ret;
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int width = cell->parameters.at(ID::Y_WIDTH).as_int();
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int offset = cell->parameters.at(ID::OFFSET).as_int();
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ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
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return ret;
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}
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if (cell->type == ID($concat)) {
|
|
RTLIL::Const ret = arg1;
|
|
ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
|
|
return ret;
|
|
}
|
|
|
|
if (cell->type == ID($lut))
|
|
{
|
|
int width = cell->parameters.at(ID::WIDTH).as_int();
|
|
|
|
std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
|
|
while (GetSize(t) < (1 << width))
|
|
t.push_back(State::S0);
|
|
t.resize(1 << width);
|
|
|
|
for (int i = width-1; i >= 0; i--) {
|
|
RTLIL::State sel = arg1.bits.at(i);
|
|
std::vector<RTLIL::State> new_t;
|
|
if (sel == State::S0)
|
|
new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
|
|
else if (sel == State::S1)
|
|
new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
|
|
else
|
|
for (int j = 0; j < GetSize(t)/2; j++)
|
|
new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
|
|
t.swap(new_t);
|
|
}
|
|
|
|
log_assert(GetSize(t) == 1);
|
|
return t;
|
|
}
|
|
|
|
if (cell->type == ID($sop))
|
|
{
|
|
int width = cell->parameters.at(ID::WIDTH).as_int();
|
|
int depth = cell->parameters.at(ID::DEPTH).as_int();
|
|
std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
|
|
|
|
while (GetSize(t) < width*depth*2)
|
|
t.push_back(State::S0);
|
|
|
|
RTLIL::State default_ret = State::S0;
|
|
|
|
for (int i = 0; i < depth; i++)
|
|
{
|
|
bool match = true;
|
|
bool match_x = true;
|
|
|
|
for (int j = 0; j < width; j++) {
|
|
RTLIL::State a = arg1.bits.at(j);
|
|
if (t.at(2*width*i + 2*j + 0) == State::S1) {
|
|
if (a == State::S1) match_x = false;
|
|
if (a != State::S0) match = false;
|
|
}
|
|
if (t.at(2*width*i + 2*j + 1) == State::S1) {
|
|
if (a == State::S0) match_x = false;
|
|
if (a != State::S1) match = false;
|
|
}
|
|
}
|
|
|
|
if (match)
|
|
return State::S1;
|
|
|
|
if (match_x)
|
|
default_ret = State::Sx;
|
|
}
|
|
|
|
return default_ret;
|
|
}
|
|
|
|
bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
|
|
bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
|
|
int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
|
|
return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
|
|
}
|
|
|
|
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
|
|
{
|
|
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
|
|
RTLIL::Const ret = arg1;
|
|
for (size_t i = 0; i < arg3.bits.size(); i++)
|
|
if (arg3.bits[i] == RTLIL::State::S1) {
|
|
std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
|
|
ret = RTLIL::Const(bits);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
if (cell->type == ID($_AOI3_))
|
|
return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
|
|
if (cell->type == ID($_OAI3_))
|
|
return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
|
|
|
|
log_assert(arg3.bits.size() == 0);
|
|
return eval(cell, arg1, arg2, errp);
|
|
}
|
|
|
|
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
|
|
{
|
|
if (cell->type == ID($_AOI4_))
|
|
return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
|
|
if (cell->type == ID($_OAI4_))
|
|
return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
|
|
|
|
log_assert(arg4.bits.size() == 0);
|
|
return eval(cell, arg1, arg2, arg3, errp);
|
|
}
|
|
};
|
|
|
|
// initialized by yosys_setup()
|
|
extern CellTypes yosys_celltypes;
|
|
|
|
YOSYS_NAMESPACE_END
|
|
|
|
#endif
|