mirror of https://github.com/YosysHQ/yosys.git
97 lines
1.2 KiB
Verilog
97 lines
1.2 KiB
Verilog
module SLE (
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output Q,
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input ADn,
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input ALn,
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input CLK,
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input D,
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input LAT,
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input SD,
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input EN,
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input SLn
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);
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reg q_latch, q_ff;
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always @(posedge CLK, negedge ALn) begin
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if (!ALn) begin
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q_ff <= !ADn;
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end else if (EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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always @* begin
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if (!ALn) begin
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q_latch <= !ADn;
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end else if (CLK && EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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assign Q = LAT ? q_latch : q_ff;
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endmodule
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module CFG1 (
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output Y,
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input A
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);
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parameter [1:0] INIT = 2'h0;
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assign Y = INIT >> A;
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endmodule
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module CFG2 (
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output Y,
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input A,
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input B
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);
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parameter [3:0] INIT = 4'h0;
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assign Y = INIT >> {B, A};
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endmodule
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module CFG3 (
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output Y,
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input A,
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input B,
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input C
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);
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parameter [7:0] INIT = 8'h0;
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assign Y = INIT >> {C, B, A};
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endmodule
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module CFG4 (
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output Y,
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input A,
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input B,
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input C,
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input D
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);
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parameter [15:0] INIT = 16'h0;
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assign Y = INIT >> {D, C, B, A};
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endmodule
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module CLKBUF (
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input PAD,
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output Y
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);
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assign Y = PAD;
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endmodule
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module INBUF (
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input PAD,
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output Y
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);
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assign Y = PAD;
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endmodule
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module OUTBUF (
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input D,
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output PAD
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);
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assign PAD = D;
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endmodule
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