This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
0bb139dc25
yosys
/
backends
/
verilog
History
Akash Levy
ace558e90c
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00