mirror of https://github.com/YosysHQ/yosys.git
14 lines
279 B
Verilog
14 lines
279 B
Verilog
module test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
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input in1, in2;
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input [1:0] vin1;
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input [3:0] vin2;
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input [1:0] vin3;
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input [3:0] vin4;
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output vout, vout1;
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output out;
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assign out = in1 && in2;
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assign vout = vin1 && vin2;
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assign vout1 = vin3 || vin4;
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endmodule
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