mirror of https://github.com/YosysHQ/yosys.git
392 lines
14 KiB
C++
392 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]]
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// Yiqiong Shi; Chan Wai Ting; Bah-Hwee Gwee; Ye Ren, "A highly efficient method for extracting FSMs from flattened gate-level netlist,"
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// Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , vol., no., pp.2610,2613, May 30 2010-June 2 2010
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// doi: 10.1109/ISCAS.2010.5537093
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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static RTLIL::Module *module;
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static SigMap assign_map;
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typedef std::pair<std::string, std::string> sig2driver_entry_t;
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static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
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static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
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{
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sig.extend(dff_out.width, false);
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if (sig == dff_out)
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return true;
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assign_map.apply(sig);
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if (sig.is_fully_const()) {
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sig.optimize();
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assert(sig.chunks.size() == 1);
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if (states.count(sig.chunks[0].data) == 0) {
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log(" found state code: %s\n", log_signal(sig));
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states[sig.chunks[0].data] = -1;
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}
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return true;
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}
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = module->cells.at(cellport.first);
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if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
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log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
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return false;
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}
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RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
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RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
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RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]);
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if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
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do {
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if (sig_a.is_fully_def())
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*reset_state = sig_a.as_const();
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else if (sig_b.is_fully_def())
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*reset_state = sig_b.as_const();
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else
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break;
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log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
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} while (0);
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if (ctrl.extract(sig_s).width == 0) {
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log(" found ctrl input: %s\n", log_signal(sig_s));
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ctrl.append(sig_s);
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}
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if (!find_states(sig_a, dff_out, ctrl, states))
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return false;
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for (int i = 0; i < sig_b.width/sig_a.width; i++) {
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if (!find_states(sig_b.extract(i*sig_a.width, sig_a.width), dff_out, ctrl, states))
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return false;
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}
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}
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return true;
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}
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static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
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{
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if (dont_care.width > 0) {
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sig.expand();
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for (auto &chunk : sig.chunks) {
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assert(chunk.width == 1);
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if (dont_care.extract(chunk).width > 0)
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chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
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}
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sig.optimize();
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}
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ce.assign_map.apply(sig);
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ce.values_map.apply(sig);
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sig.expand();
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for (auto &chunk : sig.chunks) {
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assert(chunk.width == 1);
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if (chunk.wire != NULL)
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chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
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}
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sig.optimize();
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if (sig.width == 0)
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return RTLIL::Const();
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assert(sig.chunks.size() == 1 && sig.chunks[0].wire == NULL);
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return sig.chunks[0].data;
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}
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static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care)
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{
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RTLIL::SigSpec undef, constval;
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if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) {
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assert(ctrl_out.is_fully_const() && dff_in.is_fully_const());
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FsmData::transition_t tr;
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tr.state_in = state_in;
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tr.state_out = states[ce.values_map(ce.assign_map(dff_in)).as_const()];
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tr.ctrl_in = sig2const(ce, ctrl_in, RTLIL::State::Sa, dont_care);
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tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx);
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RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
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if (state_in >= 0)
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log_state_in = fsm_data.state_table[tr.state_in];
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if (dff_in.is_fully_def()) {
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fsm_data.transition_table.push_back(tr);
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log(" transition: %10s %s -> %10s %s\n",
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log_signal(log_state_in), log_signal(tr.ctrl_in),
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log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out));
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} else {
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log(" transition: %10s %s -> %10s %s <ignored undef transistion!>\n",
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log_signal(log_state_in), log_signal(tr.ctrl_in),
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log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out));
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}
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return;
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}
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assert(undef.width > 0);
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assert(ce.stop_signals.check_all(undef));
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undef = undef.extract(0, 1);
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constval = undef;
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if (ce_nostop.eval(constval))
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{
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ce.push();
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dont_care.append(undef);
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ce.set(undef, constval.as_const());
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find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
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ce.pop();
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}
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else
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{
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ce.push(), ce_nostop.push();
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ce.set(undef, RTLIL::Const(0, 1));
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ce_nostop.set(undef, RTLIL::Const(0, 1));
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find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
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ce.pop(), ce_nostop.pop();
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ce.push(), ce_nostop.push();
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ce.set(undef, RTLIL::Const(1, 1));
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ce_nostop.set(undef, RTLIL::Const(1, 1));
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find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
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ce.pop(), ce_nostop.pop();
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}
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}
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static void extract_fsm(RTLIL::Wire *wire)
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{
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log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
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// get input and output signals for state ff
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RTLIL::SigSpec dff_out = assign_map(RTLIL::SigSpec(wire));
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RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width);
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RTLIL::Const reset_state(RTLIL::State::Sx, wire->width);
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RTLIL::SigSpec clk = RTLIL::SigSpec(0, 1);
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RTLIL::SigSpec arst = RTLIL::SigSpec(0, 1);
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bool clk_polarity = true;
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bool arst_polarity = true;
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(dff_out, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = module->cells.at(cellport.first);
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if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
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continue;
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log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
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RTLIL::SigSpec sig_q = assign_map(cell->connections["\\Q"]);
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RTLIL::SigSpec sig_d = assign_map(cell->connections["\\D"]);
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clk = cell->connections["\\CLK"];
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clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
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if (cell->type == "$adff") {
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arst = cell->connections["\\ARST"];
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arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
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reset_state = cell->parameters["\\ARST_VALUE"];
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}
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sig_q.replace(dff_out, sig_d, &dff_in);
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break;
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}
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log(" root of input selection tree: %s\n", log_signal(dff_in));
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if (dff_in.has_marked_bits()) {
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log(" fsm extraction failed: incomplete input selection tree root.\n");
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return;
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}
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// find states and control inputs
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RTLIL::SigSpec ctrl_in;
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std::map<RTLIL::Const, int> states;
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if (!arst.is_fully_const()) {
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log(" found reset state: %s (from async reset)\n", log_signal(reset_state));
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states[reset_state] = -1;
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}
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if (!find_states(dff_in, dff_out, ctrl_in, states, &reset_state)) {
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log(" fsm extraction failed: state selection tree is not closed.\n");
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return;
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}
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// find control outputs
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// (add the state signals to the list of control outputs. if everything goes right, this signals
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// become unused and can then be removed from the fsm control output)
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RTLIL::SigSpec ctrl_out = dff_in;
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cellport_list.clear();
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sig2trigger.find(dff_out, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = module->cells.at(cellport.first);
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RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
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RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
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RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]);
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if (cellport.second == "\\A" && !sig_b.is_fully_const())
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continue;
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if (cellport.second == "\\B" && !sig_a.is_fully_const())
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continue;
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log(" found ctrl output: %s\n", log_signal(sig_y));
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ctrl_out.append(sig_y);
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}
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ctrl_in.remove(ctrl_out);
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ctrl_in.sort_and_unify();
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ctrl_out.sort_and_unify();
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log(" ctrl inputs: %s\n", log_signal(ctrl_in));
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log(" ctrl outputs: %s\n", log_signal(ctrl_out));
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// Initialize fsm data struct
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FsmData fsm_data;
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fsm_data.num_inputs = ctrl_in.width;
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fsm_data.num_outputs = ctrl_out.width;
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fsm_data.state_bits = wire->width;
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fsm_data.reset_state = -1;
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for (auto &it : states) {
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it.second = fsm_data.state_table.size();
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fsm_data.state_table.push_back(it.first);
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}
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if (!arst.is_fully_const() || RTLIL::SigSpec(reset_state).is_fully_def())
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fsm_data.reset_state = states[reset_state];
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// Create transition table
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ConstEval ce(module), ce_nostop(module);
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ce.stop(ctrl_in);
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for (int state_idx = 0; state_idx < int(fsm_data.state_table.size()); state_idx++) {
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ce.push(), ce_nostop.push();
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ce.set(dff_out, fsm_data.state_table[state_idx]);
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ce_nostop.set(dff_out, fsm_data.state_table[state_idx]);
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find_transitions(ce, ce_nostop, fsm_data, states, state_idx, ctrl_in, ctrl_out, dff_in, RTLIL::SigSpec());
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ce.pop(), ce_nostop.pop();
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}
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// create fsm cell
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RTLIL::Cell *fsm_cell = new RTLIL::Cell;
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fsm_cell->name = stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++);
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fsm_cell->type = "$fsm";
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fsm_cell->connections["\\CLK"] = clk;
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fsm_cell->connections["\\ARST"] = arst;
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fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
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fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
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fsm_cell->connections["\\CTRL_IN"] = ctrl_in;
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fsm_cell->connections["\\CTRL_OUT"] = ctrl_out;
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fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
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fsm_cell->attributes = wire->attributes;
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fsm_data.copy_to_cell(fsm_cell);
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module->cells[fsm_cell->name] = fsm_cell;
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// rename original state wire
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module->wires.erase(wire->name);
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wire->attributes.erase("\\fsm_encoding");
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wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
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module->wires[wire->name] = wire;
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// unconnect control outputs from old drivers
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cellport_list.clear();
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sig2driver.find(ctrl_out, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = module->cells.at(cellport.first);
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RTLIL::SigSpec port_sig = assign_map(cell->connections[cellport.second]);
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RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
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RTLIL::Wire *unconn_wire = new RTLIL::Wire;
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unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
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unconn_wire->width = unconn_sig.width;
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module->wires[unconn_wire->name] = unconn_wire;
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port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]);
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}
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}
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struct FsmExtractPass : public Pass {
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FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_extract [selection]\n");
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log("\n");
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log("This pass operates on all signals marked as FSM state signals using the\n");
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log("'fsm_encoding' attribute. It consumes the logic that creates the state signal\n");
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log("and uses the state signal to generate control signal and replaces it with an\n");
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log("FSM cell.\n");
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log("\n");
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log("The generated FSM cell still generates the original state signal with its\n");
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log("original encoding. The 'fsm_opt' pass can be used in combination with the\n");
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log("'opt_clean' pass to eliminate this signal.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FSM_EXTRACT pass (extracting FSM from design).\n");
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extra_args(args, 1, design);
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CellTypes ct;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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for (auto &mod_it : design->modules)
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{
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if (!design->selected(mod_it.second))
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continue;
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module = mod_it.second;
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assign_map.set(module);
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sig2driver.clear();
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sig2trigger.clear();
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for (auto &cell_it : module->cells)
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for (auto &conn_it : cell_it.second->connections) {
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if (ct.cell_output(cell_it.second->type, conn_it.first)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
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}
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if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 &&
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cell_it.second->connections["\\Y"].width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
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}
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}
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std::vector<RTLIL::Wire*> wire_list;
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for (auto &wire_it : module->wires)
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if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].str != "none")
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if (design->selected(module, wire_it.second))
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wire_list.push_back(wire_it.second);
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for (auto wire : wire_list)
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extract_fsm(wire);
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}
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assign_map.clear();
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sig2driver.clear();
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sig2trigger.clear();
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}
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} FsmExtractPass;
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