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yosys/techlibs/intel_alm
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gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
 		2021-03-17 21:07:20 +00:00
..
common intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
cyclonev intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
Makefile.inc intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
synth_intel_alm.cc Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00