Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames ... s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;		2021-06-08 00:39:36 +02:00
..
tests	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Makefile.inc	synth_ice40: Use opt_dff.	2020-07-30 22:26:20 +02:00
abc9_model.v	ice40: specify fixes	2020-02-27 10:17:29 -08:00
arith_map.v	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
brams.txt	ice40: match memory inference attribute values case insensitive.	2020-02-06 14:58:20 +00:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
cells_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
cells_sim.v	Add default assignments to other SB_* simulation models	2021-04-20 18:52:36 +02:00
dsp_map.v	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	2019-08-08 12:56:05 -07:00
ff_map.v	ice40: Use dfflegalize.	2020-07-05 05:12:09 +02:00
ice40_braminit.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
ice40_opt.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
latches_map.v	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
synth_ice40.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00