yosys/techlibs/ice40
Marcelina Kościelnicka 1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
..
tests Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 2019-08-12 12:06:45 -07:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Makefile.inc ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
abc9_model.v ice40: specify fixes 2020-02-27 10:17:29 -08:00
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt ice40: match memory inference attribute values case insensitive. 2020-02-06 14:58:20 +00:00
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
dsp_map.v Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
ff_map.v ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
ice40_braminit.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ice40_ffssr.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ice40_opt.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
synth_ice40.cc ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00