mirror of https://github.com/YosysHQ/yosys.git
108 lines
3.4 KiB
C++
108 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
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{
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bool found_init = false;
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for (auto &sync : proc->syncs)
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if (sync->type == RTLIL::SyncType::STi)
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{
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found_init = true;
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log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
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for (auto &action : sync->actions)
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{
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RTLIL::SigSpec lhs = action.first;
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RTLIL::SigSpec rhs = sigmap(action.second);
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if (!rhs.is_fully_const())
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log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
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int offset = 0;
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for (auto &lhs_c : lhs.chunks())
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{
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if (lhs_c.wire != nullptr)
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{
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SigSpec valuesig = rhs.extract(offset, lhs_c.width);
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if (!valuesig.is_fully_const())
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log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
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Const value = valuesig.as_const();
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Const &wireinit = lhs_c.wire->attributes[ID::init];
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while (GetSize(wireinit.bits) < lhs_c.wire->width)
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wireinit.bits.push_back(State::Sx);
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for (int i = 0; i < lhs_c.width; i++) {
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auto &initbit = wireinit.bits[i + lhs_c.offset];
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if (initbit != State::Sx && initbit != value[i])
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log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
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initbit = value[i];
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}
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log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
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}
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offset += lhs_c.width;
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}
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}
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sync->actions.clear();
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}
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}
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struct ProcInitPass : public Pass {
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ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_init [selection]\n");
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log("\n");
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log("This pass extracts the 'init' actions from processes (generated from Verilog\n");
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log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
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log("respective wire.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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SigMap sigmap(mod);
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_init(mod, sigmap, proc_it.second);
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}
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}
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} ProcInitPass;
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PRIVATE_NAMESPACE_END
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