mirror of https://github.com/YosysHQ/yosys.git
238 lines
7.5 KiB
C++
238 lines
7.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
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{
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if (s.wire) {
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if (s.wire->width > 1)
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f << stringf(" %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
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else
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f << stringf(" %s", RTLIL::id2cstr(s.wire->name));
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} else {
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if (s == RTLIL::State::S0)
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f << stringf(" %s", neg.c_str());
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else if (s == RTLIL::State::S1)
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f << stringf(" %s", pos.c_str());
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else
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f << stringf(" %s%d", ncpf.c_str(), nc_counter++);
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}
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}
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static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian)
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{
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SigMap sigmap(module);
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int cell_counter = 0, conn_counter = 0, nc_counter = 0;
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for (auto &cell_it : module->cells_)
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{
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RTLIL::Cell *cell = cell_it.second;
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f << stringf("X%d", cell_counter++);
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std::vector<RTLIL::SigSpec> port_sigs;
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if (design->modules_.count(cell->type) == 0)
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{
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log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
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RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
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for (auto &conn : cell->connections()) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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port_sigs.push_back(sig);
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}
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}
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else
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{
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RTLIL::Module *mod = design->modules_.at(cell->type);
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std::vector<RTLIL::Wire*> ports;
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for (auto wire_it : mod->wires_) {
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_id == 0)
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continue;
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while (int(ports.size()) < wire->port_id)
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ports.push_back(NULL);
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ports.at(wire->port_id-1) = wire;
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}
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for (RTLIL::Wire *wire : ports) {
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log_assert(wire != NULL);
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RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
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if (cell->hasPort(wire->name)) {
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sig = sigmap(cell->getPort(wire->name));
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sig.extend_u0(wire->width, false);
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}
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port_sigs.push_back(sig);
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}
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}
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for (auto &sig : port_sigs) {
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for (int i = 0; i < sig.size(); i++) {
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RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
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print_spice_net(f, s, neg, pos, ncpf, nc_counter);
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}
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}
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f << stringf(" %s\n", RTLIL::id2cstr(cell->type));
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}
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for (auto &conn : module->connections())
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for (int i = 0; i < conn.first.size(); i++) {
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f << stringf("V%d", conn_counter++);
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print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
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print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);
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f << stringf(" DC 0\n");
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}
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}
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struct SpiceBackend : public Backend {
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SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_spice [options] [filename]\n");
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log("\n");
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log("Write the current design to an SPICE netlist file.\n");
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log("\n");
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log(" -big_endian\n");
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log(" generate multi-bit ports in MSB first order \n");
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log(" (default is LSB first)\n");
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log("\n");
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log(" -neg net_name\n");
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log(" set the net name for constant 0 (default: Vss)\n");
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log("\n");
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log(" -pos net_name\n");
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log(" set the net name for constant 1 (default: Vdd)\n");
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log("\n");
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log(" -nc_prefix\n");
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log(" prefix for not-connected nets (default: _NC)\n");
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log("\n");
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log(" -top top_module\n");
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log(" set the specified module as design top module\n");
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log("\n");
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module_name;
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RTLIL::Module *top_module = NULL;
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bool big_endian = false;
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std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";
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log_header("Executing SPICE backend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-big_endian") {
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big_endian = true;
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continue;
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}
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if (args[argidx] == "-neg" && argidx+1 < args.size()) {
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neg = args[++argidx];
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continue;
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}
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if (args[argidx] == "-pos" && argidx+1 < args.size()) {
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pos = args[++argidx];
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continue;
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}
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if (args[argidx] == "-nc_prefix" && argidx+1 < args.size()) {
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ncpf = args[++argidx];
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continue;
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}
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module_name = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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if (top_module_name.empty())
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for (auto & mod_it:design->modules_)
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if (mod_it.second->get_bool_attribute("\\top"))
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top_module_name = mod_it.first.str();
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*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
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*f << stringf("\n");
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for (auto module_it : design->modules_)
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{
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RTLIL::Module *module = module_it.second;
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if (module->get_bool_attribute("\\blackbox"))
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continue;
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if (module->processes.size() != 0)
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log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));
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if (module->memories.size() != 0)
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log_error("Found munmapped emories in module %s: unmapped memories are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));
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if (module->name == RTLIL::escape_id(top_module_name)) {
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top_module = module;
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continue;
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}
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std::vector<RTLIL::Wire*> ports;
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for (auto wire_it : module->wires_) {
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_id == 0)
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continue;
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while (int(ports.size()) < wire->port_id)
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ports.push_back(NULL);
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ports.at(wire->port_id-1) = wire;
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}
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*f << stringf(".SUBCKT %s", RTLIL::id2cstr(module->name));
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for (RTLIL::Wire *wire : ports) {
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log_assert(wire != NULL);
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if (wire->width > 1) {
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for (int i = 0; i < wire->width; i++)
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*f << stringf(" %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i);
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} else
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*f << stringf(" %s", RTLIL::id2cstr(wire->name));
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}
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*f << stringf("\n");
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print_spice_module(*f, module, design, neg, pos, ncpf, big_endian);
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*f << stringf(".ENDS %s\n\n", RTLIL::id2cstr(module->name));
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}
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if (!top_module_name.empty()) {
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if (top_module == NULL)
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log_error("Can't find top module `%s'!\n", top_module_name.c_str());
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print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian);
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*f << stringf("\n");
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}
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*f << stringf("************************\n");
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*f << stringf("* end of SPICE netlist *\n");
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*f << stringf("************************\n");
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*f << stringf("\n");
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}
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} SpiceBackend;
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PRIVATE_NAMESPACE_END
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