mirror of https://github.com/YosysHQ/yosys.git
165 lines
3.9 KiB
Bash
Executable File
165 lines
3.9 KiB
Bash
Executable File
#!/bin/bash
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libs=""
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genvcd=false
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use_isim=false
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verbose=false
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keeprunning=false
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backend_opts="-noattr -noexpr"
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kompare_xst=false
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scriptfiles=""
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toolsdir="$(cd $(dirname $0); pwd)"
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if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
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( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
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fi
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while getopts il:wkvrxs: opt; do
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case "$opt" in
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i)
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use_isim=true ;;
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l)
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libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
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w)
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genvcd=true ;;
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k)
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keeprunning=true ;;
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v)
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verbose=true ;;
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r)
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backend_opts="$backend_opts norename" ;;
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x)
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kompare_xst=true ;;
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s)
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[[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
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scriptfiles="$scriptfiles $OPTARG" ;;
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*)
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echo "Usage: $0 [-i] [-w] [-k] [-v] [-r] [-x] [-l libs] [-s script] verilog-files\n" >&2
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exit 1
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esac
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done
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create_ref() {
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if $kompare_xst; then
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echo "verilog work $1" > $2.prj
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cat <<- EOT > $2.xst
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run
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-ifn $2.prj -ifmt mixed -ofn $2 -ofmt NGC -p xc6slx4-3-tqg144
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-top $( grep ^module $1 | sed -r 's,[^0-9A-Za-z_]+, ,g' | awk '{ print $2; exit; }'; )
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-opt_mode Speed -opt_level 1 -iobuf NO
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EOT
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(
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set +x
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prefix="$2"
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xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
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case "$( uname -m )" in
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x86_64)
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set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;
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*)
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set --; . /opt/Xilinx/$xilver/ISE_DS/settings32.sh ;;
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esac
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set -x
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xst -ifn $prefix.xst
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netgen -w -ofmt verilog $prefix.ngc $prefix
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)
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else
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cp "$1" "$2.v"
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fi
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}
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compile_and_run() {
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exe="$1"; output="$2"; shift 2
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if $use_isim; then
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(
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set +x
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files=( "$@" )
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xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
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case "$( uname -m )" in
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x86_64)
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set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;
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*)
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set --; . /opt/Xilinx/$xilver/ISE_DS/settings32.sh ;;
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esac
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set -x
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vlogcomp "${files[@]}"
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if $kompare_xst; then
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fuse -o "$exe" -lib unisims_ver -top testbench -top glbl
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else
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fuse -o "$exe" -top testbench
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fi
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{ echo "run all"; echo "exit"; } > run-all.tcl
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PATH="$PATH:" "$exe" -tclbatch run-all.tcl > "$output"
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)
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else
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iverilog -s testbench -o "$exe" "$@"
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vvp -n "$exe" > "$output"
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fi
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}
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shift $((OPTIND - 1))
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for fn
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do
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bn=${fn%.v}
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if [ "$bn" == "$fn" ]; then
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echo "Invalid argument: $fn" >&2
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exit 1
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fi
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[[ "$bn" == *_tb ]] && continue
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echo -n "Test: $bn "
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rm -f ${bn}.{err,log}
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mkdir -p ${bn}.out
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rm -rf ${bn}.out/*
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body() {
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cd ${bn}.out
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cp ../$fn $fn
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if [ ! -f ../${bn}_tb.v ]; then
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"$toolsdir"/../../yosys -b autotest -o ${bn}_tb.v $fn
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else
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cp ../${bn}_tb.v ${bn}_tb.v
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fi
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if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
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create_ref $fn ${bn}_ref
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compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
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if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
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test_count=0
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test_passes() {
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"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
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compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
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${bn}_tb.v ${bn}_syn${test_count}.v $libs \
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"$toolsdir"/../../techlibs/simlib.v \
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"$toolsdir"/../../techlibs/stdcells_sim.v
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if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
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$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
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test_count=$(( test_count + 1 ))
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}
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if [ -n "$scriptfiles" ]; then
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test_passes
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else
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test_passes -p hierarchy -p proc -p memory -p opt -p fsm -p opt
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test_passes -p hierarchy -p proc -p memory -p opt -p fsm -p opt -p techmap -p opt
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# test_passes -p hierarchy -p proc -p memory -p opt -p techmap -p opt -p abc -p opt
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fi
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touch ../${bn}.log
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}
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if $verbose; then
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echo ".."
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echo "Output written to console." > ${bn}.err
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( set -ex; body; )
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else
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( set -ex; body; ) > ${bn}.err 2>&1
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fi
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if [ -f ${bn}.log ]; then
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mv ${bn}.err ${bn}.log
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echo "-> ok"
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else echo "-> ERROR!"; $keeprunning || exit 1; fi
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done
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exit 0
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