mirror of https://github.com/YosysHQ/yosys.git
98 lines
1.8 KiB
Verilog
98 lines
1.8 KiB
Verilog
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module test(clk, mode, u1, s1, u2, s2, y);
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input clk;
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input [5:0] mode;
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input [3:0] u1, u2;
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input signed [3:0] s1, s2;
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output reg [7:0] y;
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always @(posedge clk) begin
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y <= 8'h42;
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case (mode)
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0: y <= u1 << u2;
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1: y <= u1 << s2;
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2: y <= s1 << u2;
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3: y <= s1 << s2;
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4: y <= u1 >> u2;
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5: y <= u1 >> s2;
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6: y <= s1 >> u2;
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7: y <= s1 >> s2;
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8: y <= u1 <<< u2;
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9: y <= u1 <<< s2;
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10: y <= s1 <<< u2;
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11: y <= s1 <<< s2;
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12: y <= u1 >>> u2;
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13: y <= u1 >>> s2;
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14: y <= s1 >>> u2;
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15: y <= s1 >>> s2;
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16: y <= u1 < u2;
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17: y <= u1 < s2;
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18: y <= s1 < u2;
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19: y <= s1 < s2;
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20: y <= u1 <= u2;
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21: y <= u1 <= s2;
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22: y <= s1 <= u2;
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23: y <= s1 <= s2;
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24: y <= u1 == u2;
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25: y <= u1 == s2;
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26: y <= s1 == u2;
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27: y <= s1 == s2;
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28: y <= u1 != u2;
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29: y <= u1 != s2;
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30: y <= s1 != u2;
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31: y <= s1 != s2;
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32: y <= u1 >= u2;
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33: y <= u1 >= s2;
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34: y <= s1 >= u2;
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35: y <= s1 >= s2;
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36: y <= u1 > u2;
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37: y <= u1 > s2;
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38: y <= s1 > u2;
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39: y <= s1 > s2;
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40: y <= u1 + u2;
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41: y <= u1 + s2;
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42: y <= s1 + u2;
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43: y <= s1 + s2;
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44: y <= u1 - u2;
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45: y <= u1 - s2;
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46: y <= s1 - u2;
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47: y <= s1 - s2;
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48: y <= +u1;
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49: y <= -u1;
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50: y <= +s1;
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51: y <= -s1;
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52: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };
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53: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };
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54: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };
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55: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };
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56: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };
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57: y <= {4{u1[1:0]}};
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58: y <= {u1, u2} ^ {s1, s2};
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59: y <= {u1, u2} & {s1, s2};
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60: y <= u1[0] ? u1 : u2;
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61: y <= u1[0] ? u1 : s2;
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62: y <= u1[0] ? s1 : u2;
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63: y <= u1[0] ? s1 : s2;
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endcase
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end
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endmodule
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