mirror of https://github.com/YosysHQ/yosys.git
421 lines
20 KiB
Verilog
421 lines
20 KiB
Verilog
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_execution_unit.v
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//
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// *Module Description:
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// openMSP430 Execution unit
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module omsp_execution_unit (
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// OUTPUTs
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cpuoff, // Turns off the CPU
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dbg_reg_din, // Debug unit CPU register data input
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gie, // General interrupt enable
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mab, // Memory address bus
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mb_en, // Memory bus enable
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mb_wr, // Memory bus write transfer
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mdb_out, // Memory data bus output
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oscoff, // Turns off LFXT1 clock input
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pc_sw, // Program counter software value
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pc_sw_wr, // Program counter software write
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scg0, // System clock generator 1. Turns off the DCO
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scg1, // System clock generator 1. Turns off the SMCLK
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// INPUTs
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dbg_halt_st, // Halt/Run status from CPU
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dbg_mem_dout, // Debug unit data output
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dbg_reg_wr, // Debug unit CPU register write
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e_state, // Execution state
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exec_done, // Execution completed
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inst_ad, // Decoded Inst: destination addressing mode
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inst_as, // Decoded Inst: source addressing mode
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inst_alu, // ALU control signals
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inst_bw, // Decoded Inst: byte width
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inst_dest, // Decoded Inst: destination (one hot)
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inst_dext, // Decoded Inst: destination extended instruction word
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inst_irq_rst, // Decoded Inst: reset interrupt
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inst_jmp, // Decoded Inst: Conditional jump
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inst_mov, // Decoded Inst: mov instruction
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inst_sext, // Decoded Inst: source extended instruction word
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inst_so, // Decoded Inst: Single-operand arithmetic
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inst_src, // Decoded Inst: source (one hot)
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inst_type, // Decoded Instruction type
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mclk, // Main system clock
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mdb_in, // Memory data bus input
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pc, // Program counter
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pc_nxt, // Next PC value (for CALL & IRQ)
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puc_rst, // Main system reset
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scan_enable // Scan enable (active during scan shifting)
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);
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// OUTPUTs
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//=========
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output cpuoff; // Turns off the CPU
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output [15:0] dbg_reg_din; // Debug unit CPU register data input
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output gie; // General interrupt enable
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output [15:0] mab; // Memory address bus
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output mb_en; // Memory bus enable
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output [1:0] mb_wr; // Memory bus write transfer
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output [15:0] mdb_out; // Memory data bus output
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output oscoff; // Turns off LFXT1 clock input
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output [15:0] pc_sw; // Program counter software value
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output pc_sw_wr; // Program counter software write
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output scg0; // System clock generator 1. Turns off the DCO
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output scg1; // System clock generator 1. Turns off the SMCLK
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// INPUTs
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//=========
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input dbg_halt_st; // Halt/Run status from CPU
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input [15:0] dbg_mem_dout; // Debug unit data output
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input dbg_reg_wr; // Debug unit CPU register write
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input [3:0] e_state; // Execution state
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input exec_done; // Execution completed
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input [7:0] inst_ad; // Decoded Inst: destination addressing mode
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input [7:0] inst_as; // Decoded Inst: source addressing mode
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input [11:0] inst_alu; // ALU control signals
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input inst_bw; // Decoded Inst: byte width
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input [15:0] inst_dest; // Decoded Inst: destination (one hot)
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input [15:0] inst_dext; // Decoded Inst: destination extended instruction word
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input inst_irq_rst; // Decoded Inst: reset interrupt
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input [7:0] inst_jmp; // Decoded Inst: Conditional jump
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input inst_mov; // Decoded Inst: mov instruction
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input [15:0] inst_sext; // Decoded Inst: source extended instruction word
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input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
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input [15:0] inst_src; // Decoded Inst: source (one hot)
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input [2:0] inst_type; // Decoded Instruction type
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input mclk; // Main system clock
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input [15:0] mdb_in; // Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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input puc_rst; // Main system reset
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input scan_enable; // Scan enable (active during scan shifting)
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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wire [15:0] alu_out;
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wire [15:0] alu_out_add;
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wire [3:0] alu_stat;
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wire [3:0] alu_stat_wr;
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wire [15:0] op_dst;
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wire [15:0] op_src;
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wire [15:0] reg_dest;
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wire [15:0] reg_src;
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wire [15:0] mdb_in_bw;
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wire [15:0] mdb_in_val;
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wire [3:0] status;
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//=============================================================================
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// 2) REGISTER FILE
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//=============================================================================
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wire reg_dest_wr = ((e_state==`E_EXEC) & (
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(inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) |
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(inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) |
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inst_type[`INST_JMP])) | dbg_reg_wr;
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wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
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((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
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((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
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((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
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wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
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wire reg_sr_clr = (e_state==`E_IRQ_2);
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wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) |
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((e_state==`E_DST_WR) & inst_so[`RETI]);
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wire reg_incr = (exec_done & inst_as[`INDIR_I]) |
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((e_state==`E_SRC_RD) & inst_so[`RETI]) |
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((e_state==`E_EXEC) & inst_so[`RETI]);
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assign dbg_reg_din = reg_dest;
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omsp_register_file register_file_0 (
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// OUTPUTs
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.cpuoff (cpuoff), // Turns off the CPU
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.gie (gie), // General interrupt enable
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.pc_sw (pc_sw), // Program counter software value
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.pc_sw_wr (pc_sw_wr), // Program counter software write
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.reg_dest (reg_dest), // Selected register destination content
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.reg_src (reg_src), // Selected register source content
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.scg0 (scg0), // System clock generator 1. Turns off the DCO
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.status (status), // R2 Status {V,N,Z,C}
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// INPUTs
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.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
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.alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_dest (inst_dest), // Register destination selection
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.inst_src (inst_src), // Register source selection
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.mclk (mclk), // Main system clock
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.pc (pc), // Program counter
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.puc_rst (puc_rst), // Main system reset
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.reg_dest_val (alu_out), // Selected register destination value
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.reg_dest_wr (reg_dest_wr), // Write selected register destination
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.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
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.reg_sp_val (alu_out_add), // Stack Pointer next value
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.reg_sp_wr (reg_sp_wr), // Stack Pointer write
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.reg_sr_clr (reg_sr_clr), // Status register clear for interrupts
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.reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction
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.reg_incr (reg_incr), // Increment source register
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.scan_enable (scan_enable) // Scan enable (active during scan shifting)
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);
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//=============================================================================
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// 3) SOURCE OPERAND MUXING
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//=============================================================================
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// inst_as[`DIR] : Register direct. -> Source is in register
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// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset
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// inst_as[`INDIR] : Register indirect.
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// inst_as[`INDIR_I]: Register indirect autoincrement.
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// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x).
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// inst_as[`IMM] : Immediate (operand is next word in the instruction stream).
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// inst_as[`ABS] : Absolute (operand is in memory at address x).
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// inst_as[`CONST] : Constant.
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wire src_reg_src_sel = (e_state==`E_IRQ_0) |
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(e_state==`E_IRQ_2) |
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((e_state==`E_SRC_RD) & ~inst_as[`ABS]) |
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((e_state==`E_SRC_WR) & ~inst_as[`ABS]) |
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((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]);
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wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
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(e_state==`E_IRQ_3) |
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((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
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((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
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wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
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((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
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inst_as[`IDX] | inst_as[`SYMB] |
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inst_as[`ABS]));
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wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) |
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((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] |
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inst_so[`RETI]));
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wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] |
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inst_as[`CONST] | inst_so[`RETI]));
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assign op_src = src_reg_src_sel ? reg_src :
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src_reg_dest_sel ? reg_dest :
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src_mdb_in_val_sel ? mdb_in_val :
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src_inst_dext_sel ? inst_dext :
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src_inst_sext_sel ? inst_sext : 16'h0000;
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//=============================================================================
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// 4) DESTINATION OPERAND MUXING
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//=============================================================================
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// inst_ad[`DIR] : Register direct.
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// inst_ad[`IDX] : Register indexed.
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// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x).
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// inst_ad[`ABS] : Absolute (operand is in memory at address x).
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wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] |
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inst_as[`ABS])) |
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((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] |
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inst_as[`ABS]));
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wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) |
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((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] |
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inst_type[`INST_SO]) & ~inst_so[`RETI]);
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wire dst_fffe_sel = (e_state==`E_IRQ_0) |
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(e_state==`E_IRQ_1) |
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(e_state==`E_IRQ_3) |
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((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
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((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
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((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
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wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
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((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
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((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] |
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inst_type[`INST_SO]) & ~inst_so[`RETI]);
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assign op_dst = dbg_halt_st ? dbg_mem_dout :
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dst_inst_sext_sel ? inst_sext :
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dst_mdb_in_bw_sel ? mdb_in_bw :
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dst_reg_dest_sel ? reg_dest :
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dst_fffe_sel ? 16'hfffe : 16'h0000;
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//=============================================================================
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// 5) ALU
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//=============================================================================
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wire exec_cycle = (e_state==`E_EXEC);
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omsp_alu alu_0 (
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// OUTPUTs
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.alu_out (alu_out), // ALU output value
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.alu_out_add (alu_out_add), // ALU adder output value
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.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
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.alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
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// INPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.exec_cycle (exec_cycle), // Instruction execution cycle
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.inst_alu (inst_alu), // ALU control signals
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
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.inst_so (inst_so), // Single-operand arithmetic
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.op_dst (op_dst), // Destination operand
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.op_src (op_src), // Source operand
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.status (status) // R2 Status {V,N,Z,C}
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);
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//=============================================================================
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// 6) MEMORY INTERFACE
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//=============================================================================
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// Detect memory read/write access
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assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) |
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((e_state==`E_IRQ_3) & ~inst_irq_rst) |
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((e_state==`E_SRC_RD) & ~inst_as[`IMM]) |
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(e_state==`E_SRC_WR) |
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((e_state==`E_EXEC) & inst_so[`RETI]) |
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((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
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& ~inst_mov) |
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(e_state==`E_DST_WR);
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wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :
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~inst_bw ? 2'b11 :
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alu_out_add[0] ? 2'b10 : 2'b01;
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assign mb_wr = ({2{(e_state==`E_IRQ_1)}} |
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{2{(e_state==`E_IRQ_3)}} |
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{2{(e_state==`E_DST_WR)}} |
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{2{(e_state==`E_SRC_WR)}}) & mb_wr_msk;
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// Memory address bus
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assign mab = alu_out_add[15:0];
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// Memory data bus output
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reg [15:0] mdb_out_nxt;
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`ifdef CLOCK_GATING
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wire mdb_out_nxt_en = (e_state==`E_DST_RD) |
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(((e_state==`E_EXEC) & ~inst_so[`CALL]) |
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2));
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wire mclk_mdb_out_nxt;
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omsp_clock_gate clock_gate_mdb_out_nxt (.gclk(mclk_mdb_out_nxt),
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.clk (mclk), .enable(mdb_out_nxt_en), .scan_enable(scan_enable));
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`else
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wire mclk_mdb_out_nxt = mclk;
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`endif
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always @(posedge mclk_mdb_out_nxt or posedge puc_rst)
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if (puc_rst) mdb_out_nxt <= 16'h0000;
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else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
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`ifdef CLOCK_GATING
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else mdb_out_nxt <= alu_out;
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`else
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else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
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`endif
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assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
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// Format memory data bus input depending on BW
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reg mab_lsb;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) mab_lsb <= 1'b0;
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else if (mb_en) mab_lsb <= alu_out_add[0];
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assign mdb_in_bw = ~inst_bw ? mdb_in :
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mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
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// Memory data bus input buffer (buffer after a source read)
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reg mdb_in_buf_en;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) mdb_in_buf_en <= 1'b0;
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else mdb_in_buf_en <= (e_state==`E_SRC_RD);
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reg mdb_in_buf_valid;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) mdb_in_buf_valid <= 1'b0;
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else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
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else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
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reg [15:0] mdb_in_buf;
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`ifdef CLOCK_GATING
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wire mclk_mdb_in_buf;
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omsp_clock_gate clock_gate_mdb_in_buf (.gclk(mclk_mdb_in_buf),
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.clk (mclk), .enable(mdb_in_buf_en), .scan_enable(scan_enable));
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`else
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wire mclk_mdb_in_buf = mclk;
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`endif
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always @(posedge mclk_mdb_in_buf or posedge puc_rst)
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if (puc_rst) mdb_in_buf <= 16'h0000;
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`ifdef CLOCK_GATING
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else mdb_in_buf <= mdb_in_bw;
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`else
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else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
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`endif
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assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
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endmodule // omsp_execution_unit
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_undefines.v"
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`endif
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