mirror of https://github.com/YosysHQ/yosys.git
137 lines
3.3 KiB
Bash
Executable File
137 lines
3.3 KiB
Bash
Executable File
#!/bin/bash
|
|
|
|
libs=""
|
|
genvcd=false
|
|
use_xsim=false
|
|
use_modelsim=false
|
|
verbose=false
|
|
keeprunning=false
|
|
backend_opts="-noattr -noexpr"
|
|
scriptfiles=""
|
|
scriptopt=""
|
|
toolsdir="$(cd $(dirname $0); pwd)"
|
|
|
|
if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
|
|
( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
|
|
fi
|
|
|
|
while getopts xml:wkvrs:p: opt; do
|
|
case "$opt" in
|
|
x)
|
|
use_xsim=true ;;
|
|
m)
|
|
use_modelsim=true ;;
|
|
l)
|
|
libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
|
|
w)
|
|
genvcd=true ;;
|
|
k)
|
|
keeprunning=true ;;
|
|
v)
|
|
verbose=true ;;
|
|
r)
|
|
backend_opts="$backend_opts -norename" ;;
|
|
s)
|
|
[[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
|
|
scriptfiles="$scriptfiles $OPTARG" ;;
|
|
p)
|
|
scriptopt="$OPTARG" ;;
|
|
*)
|
|
echo "Usage: $0 [-x|-m] [-w] [-k] [-v] [-r] [-l libs] [-s script] [-p cmdstring] verilog-files\n" >&2
|
|
exit 1
|
|
esac
|
|
done
|
|
|
|
create_ref() {
|
|
cp "$1" "$2.v"
|
|
}
|
|
|
|
compile_and_run() {
|
|
exe="$1"; output="$2"; shift 2
|
|
if $use_modelsim; then
|
|
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
|
|
/opt/altera/$altver/modelsim_ase/bin/vlib work
|
|
/opt/altera/$altver/modelsim_ase/bin/vlog "$@"
|
|
/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output"
|
|
elif $use_xsim; then
|
|
(
|
|
set +x
|
|
files=( "$@" )
|
|
xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
|
|
/opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}"
|
|
/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output"
|
|
)
|
|
else
|
|
iverilog -s testbench -o "$exe" "$@"
|
|
vvp -n "$exe" > "$output"
|
|
fi
|
|
}
|
|
|
|
shift $((OPTIND - 1))
|
|
|
|
for fn
|
|
do
|
|
bn=${fn%.v}
|
|
if [ "$bn" == "$fn" ]; then
|
|
echo "Invalid argument: $fn" >&2
|
|
exit 1
|
|
fi
|
|
[[ "$bn" == *_tb ]] && continue
|
|
echo -n "Test: $bn "
|
|
|
|
rm -f ${bn}.{err,log}
|
|
mkdir -p ${bn}.out
|
|
rm -rf ${bn}.out/*
|
|
|
|
body() {
|
|
cd ${bn}.out
|
|
cp ../$fn $fn
|
|
if [ ! -f ../${bn}_tb.v ]; then
|
|
"$toolsdir"/../../yosys -b autotest -o ${bn}_tb.v $fn
|
|
else
|
|
cp ../${bn}_tb.v ${bn}_tb.v
|
|
fi
|
|
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
|
|
create_ref $fn ${bn}_ref
|
|
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
|
|
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
|
|
|
|
test_count=0
|
|
test_passes() {
|
|
"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
|
|
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
|
|
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
|
|
"$toolsdir"/../../techlibs/common/simlib.v \
|
|
"$toolsdir"/../../techlibs/common/simcells.v
|
|
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
|
|
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
|
|
test_count=$(( test_count + 1 ))
|
|
}
|
|
|
|
if [ -n "$scriptfiles" ]; then
|
|
test_passes
|
|
elif [ -n "$scriptopt" ]; then
|
|
test_passes -p "$scriptopt"
|
|
else
|
|
test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt"
|
|
test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt"
|
|
fi
|
|
touch ../${bn}.log
|
|
}
|
|
|
|
if $verbose; then
|
|
echo ".."
|
|
echo "Output written to console." > ${bn}.err
|
|
( set -ex; body; )
|
|
else
|
|
( set -ex; body; ) > ${bn}.err 2>&1
|
|
fi
|
|
|
|
if [ -f ${bn}.log ]; then
|
|
mv ${bn}.err ${bn}.log
|
|
echo "-> ok"
|
|
else echo "-> ERROR!"; $keeprunning || exit 1; fi
|
|
done
|
|
|
|
exit 0
|