mirror of https://github.com/YosysHQ/yosys.git
309 lines
8.1 KiB
C++
309 lines
8.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct proc_dlatch_db_t
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{
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Module *module;
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SigMap sigmap;
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dict<SigBit, pair<Cell*, int>> mux_drivers;
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dict<SigBit, int> sigusers;
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proc_dlatch_db_t(Module *module) : module(module), sigmap(module)
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{
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for (auto cell : module->cells())
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{
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if (cell->type.in("$mux", "$pmux")) {
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auto sig_y = sigmap(cell->getPort("\\Y"));
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for (int i = 0; i < GetSize(sig_y); i++)
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mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
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}
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for (auto &conn : cell->connections())
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if (!cell->known() || cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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sigusers[bit]++;
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}
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for (auto wire : module->wires())
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if (wire->port_input)
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for (auto bit : sigmap(wire))
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sigusers[bit]++;
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}
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struct rule_node_t
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{
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// a node is true if "signal" equals "match" and [any
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// of the child nodes is true or "children" is empty]
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SigBit signal, match;
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vector<int> children;
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bool operator==(const rule_node_t &other) const {
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return signal == other.signal && match == other.match && children == other.children;
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}
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unsigned int hash() const {
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unsigned int h = mkhash_init;
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mkhash(h, signal.hash());
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mkhash(h, match.hash());
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for (auto i : children) mkhash(h, i);
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return h;
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}
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};
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enum tf_node_types_t : int {
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true_node = 1,
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false_node = 2
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};
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idict<rule_node_t, 3> rules_db;
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dict<int, SigBit> rules_sig;
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int make_leaf(SigBit signal, SigBit match)
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{
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rule_node_t node;
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node.signal = signal;
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node.match = match;
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return rules_db(node);
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}
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int make_inner(SigBit signal, SigBit match, int child)
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{
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rule_node_t node;
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node.signal = signal;
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node.match = match;
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node.children.push_back(child);
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return rules_db(node);
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}
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int make_inner(const pool<int> &children)
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{
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rule_node_t node;
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node.signal = State::S0;
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node.match = State::S0;
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node.children = vector<int>(children.begin(), children.end());
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std::sort(node.children.begin(), node.children.end());
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return rules_db(node);
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}
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int find_mux_feedback(SigBit haystack, SigBit needle, bool set_undef)
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{
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if (sigusers[haystack] > 1)
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set_undef = false;
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if (haystack == needle)
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return true_node;
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auto it = mux_drivers.find(haystack);
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if (it == mux_drivers.end())
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return false_node;
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Cell *cell = it->second.first;
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int index = it->second.second;
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SigSpec sig_a = sigmap(cell->getPort("\\A"));
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SigSpec sig_b = sigmap(cell->getPort("\\B"));
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SigSpec sig_s = sigmap(cell->getPort("\\S"));
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int width = GetSize(sig_a);
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pool<int> children;
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int n = find_mux_feedback(sig_a[index], needle, set_undef);
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if (n != false_node) {
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if (set_undef && sig_a[index] == needle) {
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SigSpec sig = cell->getPort("\\A");
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sig[index] = State::Sx;
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cell->setPort("\\A", sig);
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}
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for (int i = 0; i < GetSize(sig_s); i++)
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n = make_inner(sig_s[i], State::S0, n);
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children.insert(n);
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}
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for (int i = 0; i < GetSize(sig_s); i++) {
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n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
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if (n != false_node) {
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if (set_undef && sig_b[i*width + index] == needle) {
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SigSpec sig = cell->getPort("\\B");
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sig[i*width + index] = State::Sx;
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cell->setPort("\\B", sig);
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}
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children.insert(make_inner(sig_s[i], State::S1, n));
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}
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}
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if (children.empty())
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return false_node;
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return make_inner(children);
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}
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SigBit make_hold(int n)
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{
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if (n == true_node)
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return State::S1;
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if (n == false_node)
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return State::S0;
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if (rules_sig.count(n))
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return rules_sig.at(n);
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const rule_node_t &rule = rules_db[n];
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SigSpec and_bits;
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if (rule.signal != rule.match) {
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if (rule.match == State::S1)
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and_bits.append(rule.signal);
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else if (rule.match == State::S0)
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and_bits.append(module->Not(NEW_ID, rule.signal));
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else
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and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match));
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}
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if (!rule.children.empty()) {
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SigSpec or_bits;
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for (int k : rule.children)
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or_bits.append(make_hold(k));
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and_bits.append(module->ReduceOr(NEW_ID, or_bits));
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}
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if (GetSize(and_bits) == 2)
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and_bits = module->And(NEW_ID, and_bits[0], and_bits[1]);
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log_assert(GetSize(and_bits) == 1);
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rules_sig[n] = and_bits[0];
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return and_bits[0];
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}
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};
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void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
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{
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std::vector<RTLIL::SyncRule*> new_syncs;
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RTLIL::SigSig latches_bits, nolatches_bits;
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dict<SigBit, SigBit> latches_out_in;
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dict<SigBit, int> latches_hold;
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for (auto sr : proc->syncs)
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{
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if (sr->type != RTLIL::SyncType::STa) {
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new_syncs.push_back(sr);
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continue;
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}
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for (auto ss : sr->actions) {
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db.sigmap.apply(ss.first);
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db.sigmap.apply(ss.second);
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for (int i = 0; i < GetSize(ss.first); i++)
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latches_out_in[ss.first[i]] = ss.second[i];
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}
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delete sr;
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}
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latches_out_in.sort();
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for (auto &it : latches_out_in) {
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int n = db.find_mux_feedback(it.second, it.first, true);
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if (n == db.false_node) {
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nolatches_bits.first.append(it.first);
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nolatches_bits.second.append(it.second);
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} else {
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latches_bits.first.append(it.first);
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latches_bits.second.append(it.second);
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latches_hold[it.first] = n;
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}
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}
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int offset = 0;
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for (auto chunk : nolatches_bits.first.chunks()) {
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SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width);
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log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
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db.module->connect(lhs, rhs);
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offset += chunk.width;
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}
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offset = 0;
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while (offset < GetSize(latches_bits.first))
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{
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int width = 1;
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int n = latches_hold[latches_bits.first[offset]];
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Wire *w = latches_bits.first[offset].wire;
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if (w != nullptr)
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{
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while (offset+width < GetSize(latches_bits.first) &&
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n == latches_hold[latches_bits.first[offset+width]] &&
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w == latches_bits.first[offset+width].wire)
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width++;
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SigSpec lhs = latches_bits.first.extract(offset, width);
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SigSpec rhs = latches_bits.second.extract(offset, width);
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Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n)), rhs, lhs);
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log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), log_id(cell));
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}
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offset += width;
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}
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new_syncs.swap(proc->syncs);
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}
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struct ProcDlatchPass : public Pass {
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ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_dlatch [selection]\n");
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log("\n");
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log("This pass identifies latches in the processes and converts them to\n");
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log("d-type latches.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing PROC_DLATCH pass (convert process syncs to latches).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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proc_dlatch_db_t db(module);
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for (auto &proc_it : module->processes)
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if (design->selected(module, proc_it.second))
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proc_dlatch(db, proc_it.second);
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}
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}
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} ProcDlatchPass;
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PRIVATE_NAMESPACE_END
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