mirror of https://github.com/YosysHQ/yosys.git
e4aa8bc96b
Before this commit, a cell's input was always assigned like:
p_cell.p_input = (value...);
If `p_input` is buffered (e.g. if the design is built at -O0), this
is not correct. (In practice, this breaks clocking.) Unfortunately,
the incorrect design was compiled without diagnostics because wire<>
was move-assignable and also implicitly constructible from value<>.
After this commit, cell inputs are no longer incorrectly assumed to
always be unbuffered, and wires are not assignable from values.
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| .. | ||
| Makefile.inc | ||
| cxxrtl.h | ||
| cxxrtl_backend.cc | ||
| cxxrtl_capi.cc | ||
| cxxrtl_capi.h | ||
| cxxrtl_vcd.h | ||
| cxxrtl_vcd_capi.cc | ||
| cxxrtl_vcd_capi.h | ||