mirror of https://github.com/YosysHQ/yosys.git
95 lines
2.0 KiB
Plaintext
95 lines
2.0 KiB
Plaintext
pattern xilinx_dsp
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state <SigBit> clock
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state <int> P_WIDTH
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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match ffA
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select ffA->type.in($dff, $dffe)
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select param(ffA, \CLK_POLARITY).as_bool()
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// select nusers(port(ffA, \Q)) == 2
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index <pool<SigBit>> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
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// DSP48E1 does not support clock inversion
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optional
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endmatch
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code clock
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if (ffA)
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clock = port(ffA, \CLK).as_bit();
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endcode
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match ffB
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select ffB->type.in($dff, $dffe)
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select param(ffB, \CLK_POLARITY).as_bool()
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// select nusers(port(ffB, \Q)) == 2
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index <pool<SigBit>> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
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optional
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endmatch
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code clock
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if (ffB) {
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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code P_WIDTH
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SigSpec P = port(dsp, \P);
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int i;
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for (i = GetSize(P); i > 0; i--)
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if (nusers(P[i-1]) > 1)
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break;
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P_WIDTH = i;
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endcode
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match ffP
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select ffP->type.in($dff, $dffe)
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select nusers(port(ffP, \D)) == 2
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filter param(ffP, \WIDTH).as_int() == P_WIDTH
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filter port(ffP, \D) == port(dsp, \P).extract(0, P_WIDTH)
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index <Const> param(ffP, \CLK_POLARITY) === State::S1
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optional
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endmatch
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// $mux cell left behind by dff2dffe
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// would prefer not to run 'opt_expr -mux_undef'
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// since that would lose information helpful for
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// efficient wide-mux inference
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match muxP
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if !ffP
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select muxP->type.in($mux)
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select port(muxP, \A).is_fully_undef()
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filter param(muxP, \WIDTH).as_int() == P_WIDTH
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filter port(muxP, \B) == port(dsp, \P).extract(0, P_WIDTH)
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select nusers(port(muxP, \B)) == 2
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optional
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endmatch
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match ffY
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if muxP
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select ffY->type.in($dff, $dffe)
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select nusers(port(ffY, \D)) == 2
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index <SigSpec> port(ffY, \D) === port(muxP, \Y)
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endmatch
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code ffP clock
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if (ffY)
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ffP = ffY;
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if (ffP) {
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SigBit c = port(ffP, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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