yosys/tests/hana/test_simulation_sop_basic_1...

15 lines
295 B
Verilog

module test(input [7:0] in, input [2:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
endcase
endmodule