This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
072604f30f
yosys
/
tests
/
hana
/
test_parse2synthtrans_param...
8 lines
89 B
Verilog
Raw
Blame
History
module
test
(
in
,
out
)
;
input
in
;
output
out
;
parameter
p
=
10
;
assign
out
=
p
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink