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module test(in, out, vin, vout, vin1, vout1, vin2, vout2);
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input in;
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input [3:0] vin, vin1, vin2;
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output [3:0] vout, vout1, vout2;
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output out;
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assign out = in << 1;
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assign vout = vin << 2;
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assign vout1 = vin1 >> 2;
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assign vout2 = vin2 >>> 2;
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endmodule
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