mirror of https://github.com/YosysHQ/yosys.git
299 lines
9.0 KiB
C++
299 lines
9.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "passes/techmap/libparse.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct statdata_t
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{
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#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
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X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
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#define STAT_NUMERIC_MEMBERS STAT_INT_MEMBERS X(area)
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#define X(_name) int _name;
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STAT_INT_MEMBERS
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#undef X
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double area;
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std::map<RTLIL::IdString, int, RTLIL::sort_by_id_str> num_cells_by_type;
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std::set<RTLIL::IdString> unknown_cell_area;
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statdata_t operator+(const statdata_t &other) const
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{
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statdata_t sum = other;
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#define X(_name) sum._name += _name;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto &it : num_cells_by_type)
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sum.num_cells_by_type[it.first] += it.second;
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return sum;
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}
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statdata_t operator*(int other) const
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{
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statdata_t sum = *this;
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#define X(_name) sum._name *= other;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto &it : sum.num_cells_by_type)
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it.second *= other;
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return sum;
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}
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statdata_t()
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{
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#define X(_name) _name = 0;
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STAT_NUMERIC_MEMBERS
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, double> &cell_area)
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{
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#define X(_name) _name = 0;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto &it : mod->wires_)
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{
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if (!design->selected(mod, it.second))
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continue;
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if (it.first[0] == '\\') {
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num_pub_wires++;
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num_pub_wire_bits += it.second->width;
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}
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num_wires++;
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num_wire_bits += it.second->width;
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}
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for (auto &it : mod->memories) {
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if (!design->selected(mod, it.second))
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continue;
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num_memories++;
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num_memory_bits += it.second->width * it.second->size;
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}
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for (auto &it : mod->cells_)
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{
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if (!design->selected(mod, it.second))
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continue;
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RTLIL::IdString cell_type = it.second->type;
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if (width_mode)
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{
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if (cell_type.in("$not", "$pos", "$neg",
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"$logic_not", "$logic_and", "$logic_or",
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"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
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"$lut", "$and", "$or", "$xor", "$xnor",
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"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) {
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int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
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int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
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int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
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cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
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}
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else if (cell_type.in("$mux", "$pmux"))
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
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else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
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}
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if (!cell_area.empty()) {
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if (cell_area.count(cell_type))
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area += cell_area.at(cell_type);
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else
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unknown_cell_area.insert(cell_type);
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}
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num_cells++;
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num_cells_by_type[cell_type]++;
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}
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for (auto &it : mod->processes) {
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if (!design->selected(mod, it.second))
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continue;
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num_processes++;
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}
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}
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void log_data(RTLIL::IdString mod_name, bool top_mod)
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{
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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log(" Number of public wires: %6d\n", num_pub_wires);
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log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
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log(" Number of memories: %6d\n", num_memories);
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log(" Number of memory bits: %6d\n", num_memory_bits);
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log(" Number of processes: %6d\n", num_processes);
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log(" Number of cells: %6d\n", num_cells);
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for (auto &it : num_cells_by_type)
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log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
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if (!unknown_cell_area.empty()) {
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log("\n");
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for (auto cell_type : unknown_cell_area)
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log(" Area for cell type %s is unknown!\n", cell_type.c_str());
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}
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if (area != 0) {
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log("\n");
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log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
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}
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}
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};
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statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
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{
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statdata_t mod_data = mod_stat.at(mod);
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std::map<RTLIL::IdString, int, RTLIL::sort_by_id_str> num_cells_by_type;
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num_cells_by_type.swap(mod_data.num_cells_by_type);
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for (auto &it : num_cells_by_type)
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if (mod_stat.count(it.first) > 0) {
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log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
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mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
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mod_data.num_cells -= it.second;
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} else {
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mod_data.num_cells_by_type[it.first] += it.second;
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}
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return mod_data;
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}
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void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_file)
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{
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std::ifstream f;
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f.open(liberty_file.c_str());
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yosys_input_files.insert(liberty_file);
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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for (auto cell : libparser.ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *ar = cell->find("area");
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if (ar != NULL && !ar->value.empty())
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cell_area["\\" + cell->args[0]] = atof(ar->value.c_str());
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}
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}
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struct StatPass : public Pass {
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StatPass() : Pass("stat", "print some statistics") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" stat [options] [selection]\n");
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log("\n");
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log("Print some statistics (number of objects) on the selected portion of the\n");
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log("design.\n");
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log("\n");
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log(" -top <module>\n");
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log(" print design hierarchy with this module as top. if the design is fully\n");
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log(" selected and a module has the 'top' attribute set, this module is used\n");
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log(" default value for this option.\n");
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log("\n");
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log(" -liberty <liberty_file>\n");
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log(" use cell area information from the provided liberty file\n");
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log("\n");
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log(" -width\n");
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log(" annotate internal cell types with their word width.\n");
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log(" e.g. $add_8 for an 8 bit wide $add cell.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Printing statistics.\n");
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bool width_mode = false;
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RTLIL::Module *top_mod = NULL;
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std::map<RTLIL::IdString, statdata_t> mod_stat;
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dict<IdString, double> cell_area;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-width") {
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width_mode = true;
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continue;
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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read_liberty_cellarea(cell_area, liberty_file);
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continue;
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}
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0)
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log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
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top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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{
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if (!top_mod && design->full_selection())
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if (mod->get_bool_attribute("\\top"))
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top_mod = mod;
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statdata_t data(design, mod, width_mode, cell_area);
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mod_stat[mod->name] = data;
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log("\n");
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log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
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log("\n");
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data.log_data(mod->name, false);
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}
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if (top_mod != NULL && GetSize(mod_stat) > 1)
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{
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log("\n");
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log("=== design hierarchy ===\n");
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log("\n");
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log(" %-28s %6d\n", RTLIL::id2cstr(top_mod->name), 1);
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statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
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log("\n");
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data.log_data(top_mod->name, true);
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}
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log("\n");
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}
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} StatPass;
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PRIVATE_NAMESPACE_END
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