mirror of https://github.com/YosysHQ/yosys.git
204 lines
6.3 KiB
C++
204 lines
6.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#include "verilog_frontend.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "libs/sha1/sha1.h"
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#include <sstream>
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#include <stdarg.h>
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#include <assert.h>
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using namespace VERILOG_FRONTEND;
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// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_verilog [filename]\n");
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log("\n");
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log("Load modules from a verilog file to the current design. A large subset of\n");
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log("Verilog-2005 is supported.\n");
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log("\n");
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log(" -dump_ast\n");
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -dump_ast_diff\n");
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log(" dump ast differences before and after simplification\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" dump ast as verilog code (after simplification)\n");
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log("\n");
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log(" -yydebug\n");
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log(" enable parser debug output\n");
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log("\n");
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log(" -nolatches\n");
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log(" usually latches are synthesized into logic loops\n");
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log(" this option prohibits this and sets the output to 'x'\n");
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log(" in what would be the latches hold condition\n");
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log("\n");
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log(" this behavior can also be achieved by setting the\n");
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log(" 'nolatches' attribute on the respective module or\n");
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log(" always block.\n");
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log("\n");
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log(" -nomem2reg\n");
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log(" under certain conditions memories are converted to registers\n");
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log(" early during simplification to ensure correct handling of\n");
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log(" complex corner cases. this option disables this behavior.\n");
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log("\n");
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log(" this can also be achieved by setting the 'nomem2reg'\n");
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log(" attribute on the respective module or register.\n");
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log("\n");
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log(" -mem2reg\n");
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log(" always convert memories to registers. this can also be\n");
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log(" achieved by setting the 'mem2reg' attribute on the respective\n");
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log(" module or register.\n");
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log("\n");
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log(" -ppdump\n");
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log(" dump verilog code after pre-processor\n");
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log("\n");
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_dump_ast = false;
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bool flag_dump_ast_diff = false;
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bool flag_dump_vlog = false;
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bool flag_nolatches = false;
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bool flag_nomem2reg = false;
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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frontend_verilog_yydebug = false;
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log_header("Executing Verilog-2005 frontend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-dump_ast") {
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flag_dump_ast = true;
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continue;
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}
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if (arg == "-dump_ast_diff") {
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flag_dump_ast = true;
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flag_dump_ast_diff = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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continue;
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}
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if (arg == "-yydebug") {
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frontend_verilog_yydebug = true;
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continue;
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}
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if (arg == "-nolatches") {
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flag_nolatches = true;
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continue;
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}
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if (arg == "-nomem2reg") {
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flag_nomem2reg = true;
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continue;
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}
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if (arg == "-mem2reg") {
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flag_mem2reg = true;
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continue;
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}
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if (arg == "-ppdump") {
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flag_ppdump = true;
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continue;
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}
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if (arg == "-nopp") {
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flag_nopp = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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log("Parsing Verilog input from `%s' to AST representation.\n", filename.c_str());
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AST::current_filename = filename;
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AST::set_line_num = &frontend_verilog_yyset_lineno;
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AST::get_line_num = &frontend_verilog_yyget_lineno;
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current_ast = new AST::AstNode(AST::AST_DESIGN);
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FILE *fp = f;
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std::string code_after_preproc;
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if (!flag_nopp) {
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code_after_preproc = frontend_verilog_preproc(f, filename);
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if (flag_ppdump)
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log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
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fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r");
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}
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lexer_feature_defattr = false;
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frontend_verilog_yyset_lineno(1);
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frontend_verilog_yyrestart(fp);
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg);
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if (!flag_nopp)
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fclose(fp);
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delete current_ast;
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current_ast = NULL;
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log("Successfully finished Verilog frontend.\n");
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}
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} VerilogFrontend;
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// the yyerror function used by bison to report parser errors
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void frontend_verilog_yyerror(char const *fmt, ...)
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{
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va_list ap;
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char buffer[1024];
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char *p = buffer;
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p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
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AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
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va_start(ap, fmt);
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p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
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va_end(ap);
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p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
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log_error("%s", buffer);
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exit(1);
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}
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