yosys/frontends/verilog
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
preproc.cc preproc: Fix up conditional handling. 2021-03-30 02:29:26 +02:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc verilog: rebuild user_type_stack from globals before parsing file 2021-03-18 20:52:36 -04:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l sv: support remaining assignment operators 2021-05-25 16:15:57 -04:00
verilog_parser.y sv: support remaining assignment operators 2021-05-25 16:15:57 -04:00