mirror of https://github.com/YosysHQ/yosys.git
22 lines
927 B
Plaintext
22 lines
927 B
Plaintext
read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -reset
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read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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