mirror of https://github.com/YosysHQ/yosys.git
24 lines
902 B
Plaintext
24 lines
902 B
Plaintext
read_verilog ../common/mul.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:MISTRAL_MUL9X9
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select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18.
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
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