mirror of https://github.com/YosysHQ/yosys.git
49 lines
879 B
Verilog
49 lines
879 B
Verilog
module abc9_test001(input a, output o);
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assign o = a;
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endmodule
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module abc9_test002(input [1:0] a, output o);
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assign o = a[1];
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endmodule
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module abc9_test003(input [1:0] a, output [1:0] o);
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assign o = a;
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endmodule
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module abc9_test004(input [1:0] a, output o);
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assign o = ^a;
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endmodule
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module abc9_test005(input [1:0] a, output o, output p);
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assign o = ^a;
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assign p = ~o;
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endmodule
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module abc9_test006(input [1:0] a, output [2:0] o);
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assign o[0] = ^a;
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assign o[1] = ~o[0];
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assign o[2] = o[1];
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endmodule
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module abc9_test007(input a, output o);
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wire b, c;
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assign c = ~a;
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assign b = c;
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abc9_test007_sub s(b, o);
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endmodule
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module abc9_test007_sub(input a, output b);
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assign b = a;
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endmodule
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module abc9_test008(input a, output o);
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wire b, c;
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assign b = ~a;
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assign c = b;
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abc9_test008_sub s(b, o);
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endmodule
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module abc9_test008_sub(input a, output b);
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assign b = ~a;
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endmodule
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