mirror of https://github.com/YosysHQ/yosys.git
26 lines
585 B
Verilog
26 lines
585 B
Verilog
module sevenseg ( output reg [6:0] HEX0,
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input [3:0] SW );
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always @(*) begin
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case(SW)
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4'h1: HEX0 = 7'b1111001;
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4'h2: HEX0 = 7'b0100100;
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4'h3: HEX0 = 7'b0110000;
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4'h4: HEX0 = 7'b0011001;
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4'h5: HEX0 = 7'b0010010;
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4'h6: HEX0 = 7'b0000010;
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4'h7: HEX0 = 7'b1111000;
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4'h8: HEX0 = 7'b0000000;
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4'h9: HEX0 = 7'b0011000;
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4'ha: HEX0 = 7'b0001000;
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4'hb: HEX0 = 7'b0000011;
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4'hc: HEX0 = 7'b1000110;
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4'hd: HEX0 = 7'b0100001;
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4'he: HEX0 = 7'b0000110;
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4'hf: HEX0 = 7'b0001110;
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4'h0: HEX0 = 7'b1000000;
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endcase // case (SW)
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end
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endmodule
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