mirror of https://github.com/YosysHQ/yosys.git
f2c2d73f36
- disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label |
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.. | ||
.gitignore | ||
Makefile.inc | ||
const2ast.cc | ||
preproc.cc | ||
preproc.h | ||
verilog_frontend.cc | ||
verilog_frontend.h | ||
verilog_lexer.l | ||
verilog_parser.y |