mirror of https://github.com/YosysHQ/yosys.git
82 lines
2.4 KiB
C++
82 lines
2.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct BlackboxPass : public Pass {
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BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" blackbox [options] [selection]\n");
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log("\n");
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log("Convert modules into blackbox modules (remove contents and set the blackbox\n");
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log("module attribute).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-???") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_whole_modules_warn())
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{
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pool<Cell*> remove_cells;
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pool<Wire*> remove_wires;
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for (auto cell : module->cells())
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remove_cells.insert(cell);
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for (auto wire : module->wires())
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if (wire->port_id == 0)
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remove_wires.insert(wire);
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for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
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delete it->second;
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module->memories.clear();
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for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
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delete it->second;
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module->processes.clear();
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module->new_connections(std::vector<RTLIL::SigSig>());
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for (auto cell : remove_cells)
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module->remove(cell);
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module->remove(remove_wires);
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module->set_bool_attribute("\\blackbox");
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}
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}
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} BlackboxPass;
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PRIVATE_NAMESPACE_END
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