mirror of https://github.com/YosysHQ/yosys.git
100 lines
2.9 KiB
C++
100 lines
2.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/demo_reduce_pm.h"
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void create_reduce(demo_reduce_pm &pm)
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{
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auto &st = pm.st_reduce;
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auto &ud = pm.ud_reduce;
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if (ud.longest_chain.empty())
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return;
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log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
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SigSpec A;
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SigSpec Y = ud.longest_chain.front().first->getPort(ID(Y));
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auto last_cell = ud.longest_chain.back().first;
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for (auto it : ud.longest_chain) {
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auto cell = it.first;
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if (cell == last_cell) {
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A.append(cell->getPort(ID(A)));
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A.append(cell->getPort(ID(B)));
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} else {
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A.append(cell->getPort(it.second == ID(A) ? ID(B) : ID(A)));
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}
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log(" %s\n", log_id(cell));
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pm.autoremove(cell);
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}
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Cell *c;
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if (last_cell->type == ID($_AND_))
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c = pm.module->addReduceAnd(NEW_ID, A, Y);
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else if (last_cell->type == ID($_OR_))
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c = pm.module->addReduceOr(NEW_ID, A, Y);
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else if (last_cell->type == ID($_XOR_))
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c = pm.module->addReduceXor(NEW_ID, A, Y);
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else
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log_abort();
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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struct DemoReducePass : public Pass {
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DemoReducePass() : Pass("demo_reduce", "map chains of AND/OR/XOR") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" demo_reduce [options] [selection]\n");
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log("\n");
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log("Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing DEMO_REDUCE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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demo_reduce_pm(module, module->selected_cells()).run_reduce(create_reduce);
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}
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} DemoReducePass;
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PRIVATE_NAMESPACE_END
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