mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.3 KiB
Verilog
60 lines
1.3 KiB
Verilog
module \$__MUL32X18 (input [31:0] A, input [17:0] B, output [49:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 32;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 50;
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dspv2_32x18x64_cfg_ports _TECHMAP_REPLACE_ (
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.a_i(A),
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.b_i(B),
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.c_i(18'd0),
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.z_o(Y),
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.clock_i(1'bx),
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.reset_i(1'bx),
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.acc_reset_i(1'b0),
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.feedback_i(3'd0),
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.load_acc_i(1'b0),
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.output_select_i(3'd0),
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.a_cin_i(32'dx),
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.b_cin_i(18'dx),
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.z_cin_i(50'dx),
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/* TODO: connect to dummy wires?
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.a_cout_o(),
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.b_cout_o(),
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.z_cout_o(),
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*/
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);
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endmodule
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module \$__MUL16X9 (input [15:0] A, input [8:0] B, output [24:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 16;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 25;
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dspv2_16x9x32_cfg_ports _TECHMAP_REPLACE_ (
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.a_i(A),
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.b_i(B),
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.c_i(10'd0),
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.z_o(Y),
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.clock_i(1'bx),
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.reset_i(1'bx),
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.acc_reset_i(1'b0),
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.feedback_i(3'd0),
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.load_acc_i(1'b0),
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.output_select_i(3'd0),
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.a_cin_i(32'dx),
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.b_cin_i(18'dx),
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.z_cin_i(50'dx),
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/* TODO: connect to dummy wires?
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.a_cout_o(),
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.b_cout_o(),
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.z_cout_o(),
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*/
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);
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endmodule
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