mirror of https://github.com/YosysHQ/yosys.git
128 lines
3.9 KiB
ReStructuredText
128 lines
3.9 KiB
ReStructuredText
Mapping to cell libraries
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-------------------------
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.. role:: yoscrypt(code)
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:language: yoscrypt
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While much of this documentation focuses on the use of Yosys with FPGAs, it is
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also possible to map to cell libraries which can be used in designing ASICs.
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This section will cover a brief `example project`_, available in the Yosys
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source code under :file:`docs/source/code_examples/intro/`. The project
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contains a simple ASIC synthesis script (:file:`counter.ys`), a digital design
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written in Verilog (:file:`counter.v`), and a simple CMOS cell library
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(:file:`mycells.lib`). Many of the early steps here are already covered in more
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detail in the :doc:`/getting_started/example_synth` document.
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.. note::
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The :file:`counter.ys` script includes the commands used to generate the
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images in this document. Code snippets in this document skip these commands;
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including line numbers to allow the reader to follow along with the source.
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To learn more about these commands, check out :ref:`interactive_show`.
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.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
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A simple counter
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~~~~~~~~~~~~~~~~
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First, let's quickly look at the design:
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.. literalinclude:: /code_examples/intro/counter.v
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:language: Verilog
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:linenos:
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:name: counter-v
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:caption: :file:`counter.v`
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This is a simple counter with reset and enable. If the reset signal, ``rst``,
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is high then the counter will reset to 0. Otherwise, if the enable signal,
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``en``, is high then the ``count`` register will increment by 1 each rising edge
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of the clock, ``clk``.
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Loading the design
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~~~~~~~~~~~~~~~~~~
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 1-3
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:lineno-match:
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:caption: :file:`counter.ys` - read design
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Our circuit now looks like this:
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.. figure:: /_images/code_examples/intro/counter_00.*
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:class: width-helper invert-helper
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:name: counter-hierarchy
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``counter`` after `hierarchy`
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Coarse-grain representation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 7-10
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:lineno-match:
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:caption: :file:`counter.ys` - the high-level stuff
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.. figure:: /_images/code_examples/intro/counter_01.*
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:class: width-helper invert-helper
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Coarse-grain representation of the ``counter`` module
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Logic gate mapping
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~~~~~~~~~~~~~~~~~~
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 14-15
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:lineno-match:
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:caption: :file:`counter.ys` - mapping to internal cell library
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.. figure:: /_images/code_examples/intro/counter_02.*
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:class: width-helper invert-helper
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``counter`` after `techmap`
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Mapping to hardware
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~~~~~~~~~~~~~~~~~~~
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For this example, we are using a Liberty file to describe a cell library which
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our internal cell library will be mapped to:
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.. todo:: find a Liberty pygments style?
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.. literalinclude:: /code_examples/intro/mycells.lib
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:language: text
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:linenos:
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:name: mycells-lib
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:caption: :file:`mycells.lib`
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Recall that the Yosys built-in logic gate types are `$_NOT_`, `$_AND_`, `$_OR_`,
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`$_XOR_`, and `$_MUX_` with an assortment of dff memory types.
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:ref:`mycells-lib` defines our target cells as ``BUF``, ``NOT``, ``NAND``,
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``NOR``, and ``DFF``. Mapping between these is performed with the commands
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`dfflibmap` and `abc` as follows:
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 20-27
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:lineno-match:
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:caption: :file:`counter.ys` - mapping to hardware
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The final version of our ``counter`` module looks like this:
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.. figure:: /_images/code_examples/intro/counter_03.*
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:class: width-helper invert-helper
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``counter`` after hardware cell mapping
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Before finally being output as a verilog file with `write_verilog`, which can
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then be loaded into another tool:
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 30-31
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:lineno-match:
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:caption: :file:`counter.ys` - write synthesized design
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